Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 3 | * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger |
| 4 | * Copyright (C) 2011 Stefan Tauner |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 5 | * Copyright (C) 2018 Siemens AG |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 6 | * |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but without any warranty; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
Arthur Heymans | 026863b | 2019-11-21 08:24:02 +0100 | [diff] [blame^] | 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 20 | /* This file is derived from the flashrom project. */ |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 21 | #include <arch/early_variables.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 22 | #include <stdint.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <string.h> |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 25 | #include <bootstate.h> |
Furquan Shaikh | de705fa | 2017-04-19 19:27:28 -0700 | [diff] [blame] | 26 | #include <commonlib/helpers.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 27 | #include <delay.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 28 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 29 | #include <device/pci_ops.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 30 | #include <console/console.h> |
Kyösti Mälkki | 7ba1440 | 2019-02-07 12:44:00 +0200 | [diff] [blame] | 31 | #include <device/device.h> |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 32 | #include <device/pci.h> |
| 33 | #include <spi_flash.h> |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 34 | #include <spi-generic.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 35 | |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 36 | #include "spi.h" |
| 37 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 38 | #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ |
| 39 | #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) |
| 40 | #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ |
| 41 | #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) |
| 42 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 43 | static int spi_is_multichip(void); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 44 | |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 45 | struct ich7_spi_regs { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 46 | uint16_t spis; |
| 47 | uint16_t spic; |
| 48 | uint32_t spia; |
| 49 | uint64_t spid[8]; |
| 50 | uint64_t _pad; |
| 51 | uint32_t bbar; |
| 52 | uint16_t preop; |
| 53 | uint16_t optype; |
| 54 | uint8_t opmenu[8]; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 55 | uint32_t pbr[3]; |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 56 | } __packed; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 57 | |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 58 | struct ich9_spi_regs { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 59 | uint32_t bfpr; |
| 60 | uint16_t hsfs; |
| 61 | uint16_t hsfc; |
| 62 | uint32_t faddr; |
| 63 | uint32_t _reserved0; |
| 64 | uint32_t fdata[16]; |
| 65 | uint32_t frap; |
| 66 | uint32_t freg[5]; |
| 67 | uint32_t _reserved1[3]; |
| 68 | uint32_t pr[5]; |
| 69 | uint32_t _reserved2[2]; |
| 70 | uint8_t ssfs; |
| 71 | uint8_t ssfc[3]; |
| 72 | uint16_t preop; |
| 73 | uint16_t optype; |
| 74 | uint8_t opmenu[8]; |
| 75 | uint32_t bbar; |
| 76 | uint8_t _reserved3[12]; |
| 77 | uint32_t fdoc; |
| 78 | uint32_t fdod; |
| 79 | uint8_t _reserved4[8]; |
| 80 | uint32_t afc; |
| 81 | uint32_t lvscc; |
| 82 | uint32_t uvscc; |
| 83 | uint8_t _reserved5[4]; |
| 84 | uint32_t fpb; |
| 85 | uint8_t _reserved6[28]; |
| 86 | uint32_t srdl; |
| 87 | uint32_t srdc; |
| 88 | uint32_t srd; |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 89 | } __packed; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 90 | |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 91 | struct ich_spi_controller { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 92 | int locked; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 93 | uint32_t flmap0; |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 94 | uint32_t flcomp; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 95 | uint32_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 96 | |
Arthur Heymans | 21c5d43 | 2019-06-15 18:23:29 +0200 | [diff] [blame] | 97 | union { |
| 98 | struct ich9_spi_regs *ich9_spi; |
| 99 | struct ich7_spi_regs *ich7_spi; |
| 100 | }; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 101 | uint8_t *opmenu; |
| 102 | int menubytes; |
| 103 | uint16_t *preop; |
| 104 | uint16_t *optype; |
| 105 | uint32_t *addr; |
| 106 | uint8_t *data; |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 107 | unsigned int databytes; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 108 | uint8_t *status; |
| 109 | uint16_t *control; |
| 110 | uint32_t *bbar; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 111 | uint32_t *fpr; |
| 112 | uint8_t fpr_max; |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 113 | }; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 114 | |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 115 | static struct ich_spi_controller g_cntlr CAR_GLOBAL; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 116 | |
| 117 | enum { |
| 118 | SPIS_SCIP = 0x0001, |
| 119 | SPIS_GRANT = 0x0002, |
| 120 | SPIS_CDS = 0x0004, |
| 121 | SPIS_FCERR = 0x0008, |
| 122 | SSFS_AEL = 0x0010, |
| 123 | SPIS_LOCK = 0x8000, |
| 124 | SPIS_RESERVED_MASK = 0x7ff0, |
| 125 | SSFS_RESERVED_MASK = 0x7fe2 |
| 126 | }; |
| 127 | |
| 128 | enum { |
| 129 | SPIC_SCGO = 0x000002, |
| 130 | SPIC_ACS = 0x000004, |
| 131 | SPIC_SPOP = 0x000008, |
| 132 | SPIC_DBC = 0x003f00, |
| 133 | SPIC_DS = 0x004000, |
| 134 | SPIC_SME = 0x008000, |
| 135 | SSFC_SCF_MASK = 0x070000, |
| 136 | SSFC_RESERVED = 0xf80000 |
| 137 | }; |
| 138 | |
| 139 | enum { |
| 140 | HSFS_FDONE = 0x0001, |
| 141 | HSFS_FCERR = 0x0002, |
| 142 | HSFS_AEL = 0x0004, |
| 143 | HSFS_BERASE_MASK = 0x0018, |
| 144 | HSFS_BERASE_SHIFT = 3, |
| 145 | HSFS_SCIP = 0x0020, |
| 146 | HSFS_FDOPSS = 0x2000, |
| 147 | HSFS_FDV = 0x4000, |
| 148 | HSFS_FLOCKDN = 0x8000 |
| 149 | }; |
| 150 | |
| 151 | enum { |
| 152 | HSFC_FGO = 0x0001, |
| 153 | HSFC_FCYCLE_MASK = 0x0006, |
| 154 | HSFC_FCYCLE_SHIFT = 1, |
| 155 | HSFC_FDBC_MASK = 0x3f00, |
| 156 | HSFC_FDBC_SHIFT = 8, |
| 157 | HSFC_FSMIE = 0x8000 |
| 158 | }; |
| 159 | |
| 160 | enum { |
| 161 | SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| 162 | SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| 163 | SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| 164 | SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| 165 | }; |
| 166 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 167 | #if CONFIG(DEBUG_SPI_FLASH) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 168 | |
| 169 | static u8 readb_(const void *addr) |
| 170 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 171 | u8 v = read8(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 172 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 173 | printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 174 | v, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 175 | return v; |
| 176 | } |
| 177 | |
| 178 | static u16 readw_(const void *addr) |
| 179 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 180 | u16 v = read16(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 181 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 182 | printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 183 | v, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 184 | return v; |
| 185 | } |
| 186 | |
| 187 | static u32 readl_(const void *addr) |
| 188 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 189 | u32 v = read32(addr); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 190 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 191 | printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 192 | v, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 193 | return v; |
| 194 | } |
| 195 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 196 | static void writeb_(u8 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 197 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 198 | write8(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 199 | printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 200 | b, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 201 | } |
| 202 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 203 | static void writew_(u16 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 204 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 205 | write16(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 206 | printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 207 | b, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 208 | } |
| 209 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 210 | static void writel_(u32 b, void *addr) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 211 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 212 | write32(addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 213 | printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 214 | b, ((unsigned int) addr & 0xffff) - 0xf020); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ |
| 218 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 219 | #define readb_(a) read8(a) |
| 220 | #define readw_(a) read16(a) |
| 221 | #define readl_(a) read32(a) |
| 222 | #define writeb_(val, addr) write8(addr, val) |
| 223 | #define writew_(val, addr) write16(addr, val) |
| 224 | #define writel_(val, addr) write32(addr, val) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 225 | |
| 226 | #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ |
| 227 | |
| 228 | static void write_reg(const void *value, void *dest, uint32_t size) |
| 229 | { |
| 230 | const uint8_t *bvalue = value; |
| 231 | uint8_t *bdest = dest; |
| 232 | |
| 233 | while (size >= 4) { |
| 234 | writel_(*(const uint32_t *)bvalue, bdest); |
| 235 | bdest += 4; bvalue += 4; size -= 4; |
| 236 | } |
| 237 | while (size) { |
| 238 | writeb_(*bvalue, bdest); |
| 239 | bdest++; bvalue++; size--; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | static void read_reg(const void *src, void *value, uint32_t size) |
| 244 | { |
| 245 | const uint8_t *bsrc = src; |
| 246 | uint8_t *bvalue = value; |
| 247 | |
| 248 | while (size >= 4) { |
| 249 | *(uint32_t *)bvalue = readl_(bsrc); |
| 250 | bsrc += 4; bvalue += 4; size -= 4; |
| 251 | } |
| 252 | while (size) { |
| 253 | *bvalue = readb_(bsrc); |
| 254 | bsrc++; bvalue++; size--; |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | static void ich_set_bbar(uint32_t minaddr) |
| 259 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 260 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 261 | const uint32_t bbar_mask = 0x00ffff00; |
| 262 | uint32_t ichspi_bbar; |
| 263 | |
| 264 | minaddr &= bbar_mask; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 265 | ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 266 | ichspi_bbar |= minaddr; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 267 | writel_(ichspi_bbar, cntlr->bbar); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 268 | } |
| 269 | |
Jacob Garber | 9172b69 | 2019-06-26 16:18:16 -0600 | [diff] [blame] | 270 | #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) |
| 271 | #define MENU_BYTES member_size(struct ich7_spi_regs, opmenu) |
| 272 | #else |
| 273 | #define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) |
| 274 | #endif |
| 275 | |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 276 | #define RCBA 0xf0 |
| 277 | #define SBASE 0x54 |
| 278 | |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 279 | static void *get_spi_bar(pci_devfn_t dev) |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 280 | { |
| 281 | uintptr_t rcba; /* Root Complex Register Block */ |
| 282 | uintptr_t sbase; |
| 283 | |
| 284 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { |
| 285 | rcba = pci_read_config32(dev, RCBA); |
| 286 | return (void *)((rcba & 0xffffc000) + 0x3020); |
| 287 | } |
| 288 | if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT)) { |
| 289 | sbase = pci_read_config32(dev, SBASE); |
| 290 | sbase &= ~0x1ff; |
| 291 | return (void *)sbase; |
| 292 | } |
| 293 | if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { |
| 294 | rcba = pci_read_config32(dev, RCBA); |
| 295 | return (void *)((rcba & 0xffffc000) + 0x3800); |
| 296 | } |
| 297 | } |
| 298 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 299 | void spi_init(void) |
| 300 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 301 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 302 | uint8_t bios_cntl; |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 303 | struct ich9_spi_regs *ich9_spi; |
| 304 | struct ich7_spi_regs *ich7_spi; |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 305 | uint16_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 306 | |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 307 | pci_devfn_t dev = PCI_DEV(0, 31, 0); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 308 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 309 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 310 | ich7_spi = get_spi_bar(dev); |
Arthur Heymans | 21c5d43 | 2019-06-15 18:23:29 +0200 | [diff] [blame] | 311 | cntlr->ich7_spi = ich7_spi; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 312 | cntlr->opmenu = ich7_spi->opmenu; |
| 313 | cntlr->menubytes = sizeof(ich7_spi->opmenu); |
| 314 | cntlr->optype = &ich7_spi->optype; |
| 315 | cntlr->addr = &ich7_spi->spia; |
| 316 | cntlr->data = (uint8_t *)ich7_spi->spid; |
| 317 | cntlr->databytes = sizeof(ich7_spi->spid); |
| 318 | cntlr->status = (uint8_t *)&ich7_spi->spis; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 319 | cntlr->control = &ich7_spi->spic; |
| 320 | cntlr->bbar = &ich7_spi->bbar; |
| 321 | cntlr->preop = &ich7_spi->preop; |
| 322 | cntlr->fpr = &ich7_spi->pbr[0]; |
| 323 | cntlr->fpr_max = 3; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 324 | } else { |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 325 | ich9_spi = get_spi_bar(dev); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 326 | cntlr->ich9_spi = ich9_spi; |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 327 | hsfs = readw_(&ich9_spi->hsfs); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 328 | cntlr->hsfs = hsfs; |
| 329 | cntlr->opmenu = ich9_spi->opmenu; |
| 330 | cntlr->menubytes = sizeof(ich9_spi->opmenu); |
| 331 | cntlr->optype = &ich9_spi->optype; |
| 332 | cntlr->addr = &ich9_spi->faddr; |
| 333 | cntlr->data = (uint8_t *)ich9_spi->fdata; |
| 334 | cntlr->databytes = sizeof(ich9_spi->fdata); |
| 335 | cntlr->status = &ich9_spi->ssfs; |
| 336 | cntlr->control = (uint16_t *)ich9_spi->ssfc; |
| 337 | cntlr->bbar = &ich9_spi->bbar; |
| 338 | cntlr->preop = &ich9_spi->preop; |
| 339 | cntlr->fpr = &ich9_spi->pr[0]; |
| 340 | cntlr->fpr_max = 5; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 341 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 342 | if (cntlr->hsfs & HSFS_FDV) { |
Patrick Georgi | c88828d | 2018-11-26 10:42:59 +0100 | [diff] [blame] | 343 | writel_(4, &ich9_spi->fdoc); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 344 | cntlr->flmap0 = readl_(&ich9_spi->fdod); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 345 | writel_(0x1000, &ich9_spi->fdoc); |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 346 | cntlr->flcomp = readl_(&ich9_spi->fdod); |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 347 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 348 | } |
| 349 | |
| 350 | ich_set_bbar(0); |
| 351 | |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 352 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { |
| 353 | /* Disable the BIOS write protect so write commands are allowed. */ |
| 354 | bios_cntl = pci_read_config8(dev, 0xdc); |
| 355 | /* Deassert SMM BIOS Write Protect Disable. */ |
| 356 | bios_cntl &= ~(1 << 5); |
| 357 | pci_write_config8(dev, 0xdc, bios_cntl | 0x1); |
| 358 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 359 | } |
Aaron Durbin | 4d3de7e | 2015-09-02 17:34:04 -0500 | [diff] [blame] | 360 | |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 361 | static int spi_locked(void) |
| 362 | { |
| 363 | struct ich_spi_controller *cntlr = &g_cntlr; |
| 364 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { |
| 365 | return !!(readw_(&cntlr->ich7_spi->spis) & HSFS_FLOCKDN); |
| 366 | } else { |
Jacob Garber | 3674974 | 2019-07-02 11:08:53 -0600 | [diff] [blame] | 367 | return !!(readw_(&cntlr->ich9_spi->hsfs) & HSFS_FLOCKDN); |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 368 | } |
| 369 | } |
| 370 | |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame] | 371 | static void spi_init_cb(void *unused) |
| 372 | { |
| 373 | spi_init(); |
| 374 | } |
| 375 | |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame] | 376 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 377 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 378 | typedef struct spi_transaction { |
| 379 | const uint8_t *out; |
| 380 | uint32_t bytesout; |
| 381 | uint8_t *in; |
| 382 | uint32_t bytesin; |
| 383 | uint8_t type; |
| 384 | uint8_t opcode; |
| 385 | uint32_t offset; |
| 386 | } spi_transaction; |
| 387 | |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 388 | static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 389 | { |
| 390 | trans->out += bytes; |
| 391 | trans->bytesout -= bytes; |
| 392 | } |
| 393 | |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 394 | static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 395 | { |
| 396 | trans->in += bytes; |
| 397 | trans->bytesin -= bytes; |
| 398 | } |
| 399 | |
| 400 | static void spi_setup_type(spi_transaction *trans) |
| 401 | { |
| 402 | trans->type = 0xFF; |
| 403 | |
| 404 | /* Try to guess spi type from read/write sizes. */ |
| 405 | if (trans->bytesin == 0) { |
| 406 | if (trans->bytesout > 4) |
| 407 | /* |
| 408 | * If bytesin = 0 and bytesout > 4, we presume this is |
| 409 | * a write data operation, which is accompanied by an |
| 410 | * address. |
| 411 | */ |
| 412 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
| 413 | else |
| 414 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 415 | return; |
| 416 | } |
| 417 | |
| 418 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
| 419 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 420 | return; |
| 421 | } |
| 422 | |
| 423 | if (trans->bytesout == 4) { /* and bytesin is > 0 */ |
| 424 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 425 | } |
Duncan Laurie | 23b0053 | 2012-10-10 14:21:23 -0700 | [diff] [blame] | 426 | |
| 427 | /* Fast read command is called with 5 bytes instead of 4 */ |
| 428 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { |
| 429 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 430 | --trans->bytesout; |
| 431 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | static int spi_setup_opcode(spi_transaction *trans) |
| 435 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 436 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 437 | uint16_t optypes; |
Jacob Garber | 9172b69 | 2019-06-26 16:18:16 -0600 | [diff] [blame] | 438 | uint8_t opmenu[MENU_BYTES]; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 439 | |
| 440 | trans->opcode = trans->out[0]; |
| 441 | spi_use_out(trans, 1); |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 442 | if (!spi_locked()) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 443 | /* The lock is off, so just use index 0. */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 444 | writeb_(trans->opcode, cntlr->opmenu); |
| 445 | optypes = readw_(cntlr->optype); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 446 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 447 | writew_(optypes, cntlr->optype); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 448 | return 0; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 449 | } |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 450 | |
| 451 | /* The lock is on. See if what we need is on the menu. */ |
| 452 | uint8_t optype; |
| 453 | uint16_t opcode_index; |
| 454 | |
| 455 | /* Write Enable is handled as atomic prefix */ |
| 456 | if (trans->opcode == SPI_OPCODE_WREN) |
| 457 | return 0; |
| 458 | |
| 459 | read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); |
Jacob Garber | 9172b69 | 2019-06-26 16:18:16 -0600 | [diff] [blame] | 460 | for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 461 | if (opmenu[opcode_index] == trans->opcode) |
| 462 | break; |
| 463 | } |
| 464 | |
Jacob Garber | 9172b69 | 2019-06-26 16:18:16 -0600 | [diff] [blame] | 465 | if (opcode_index == ARRAY_SIZE(opmenu)) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 466 | printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", |
| 467 | trans->opcode); |
| 468 | return -1; |
| 469 | } |
| 470 | |
| 471 | optypes = readw_(cntlr->optype); |
| 472 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
| 473 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
| 474 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
| 475 | trans->bytesout >= 3) { |
| 476 | /* We guessed wrong earlier. Fix it up. */ |
| 477 | trans->type = optype; |
| 478 | } |
| 479 | if (optype != trans->type) { |
| 480 | printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", |
| 481 | optype); |
| 482 | return -1; |
| 483 | } |
| 484 | return opcode_index; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 485 | } |
| 486 | |
| 487 | static int spi_setup_offset(spi_transaction *trans) |
| 488 | { |
| 489 | /* Separate the SPI address and data. */ |
| 490 | switch (trans->type) { |
| 491 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
| 492 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
| 493 | return 0; |
| 494 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
| 495 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
| 496 | trans->offset = ((uint32_t)trans->out[0] << 16) | |
| 497 | ((uint32_t)trans->out[1] << 8) | |
| 498 | ((uint32_t)trans->out[2] << 0); |
| 499 | spi_use_out(trans, 3); |
| 500 | return 1; |
| 501 | default: |
| 502 | printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); |
| 503 | return -1; |
| 504 | } |
| 505 | } |
| 506 | |
| 507 | /* |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 508 | * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 509 | * below is True) or 0. In case the wait was for the bit(s) to set - write |
| 510 | * those bits back, which would cause resetting them. |
| 511 | * |
| 512 | * Return the last read status value on success or -1 on failure. |
| 513 | */ |
| 514 | static int ich_status_poll(u16 bitmask, int wait_til_set) |
| 515 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 516 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 517 | int timeout = 600000; /* This will result in 6 seconds */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 518 | u16 status = 0; |
| 519 | |
| 520 | while (timeout--) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 521 | status = readw_(cntlr->status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 522 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
| 523 | if (wait_til_set) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 524 | writew_((status & bitmask), cntlr->status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 525 | return status; |
| 526 | } |
| 527 | udelay(10); |
| 528 | } |
| 529 | |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 530 | printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n", |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 531 | status, bitmask); |
| 532 | return -1; |
| 533 | } |
| 534 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 535 | static int spi_is_multichip(void) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 536 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 537 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 538 | if (!(cntlr->hsfs & HSFS_FDV)) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 539 | return 0; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 540 | return !!((cntlr->flmap0 >> 8) & 3); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 541 | } |
| 542 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 543 | static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 544 | size_t bytesout, void *din, size_t bytesin) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 545 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 546 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 547 | uint16_t control; |
| 548 | int16_t opcode_index; |
| 549 | int with_address; |
| 550 | int status; |
| 551 | |
| 552 | spi_transaction trans = { |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 553 | dout, bytesout, |
| 554 | din, bytesin, |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 555 | 0xff, 0xff, 0 |
| 556 | }; |
| 557 | |
| 558 | /* There has to always at least be an opcode. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 559 | if (!bytesout || !dout) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 560 | printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); |
| 561 | return -1; |
| 562 | } |
| 563 | /* Make sure if we read something we have a place to put it. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 564 | if (bytesin != 0 && !din) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 565 | printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); |
| 566 | return -1; |
| 567 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 568 | |
| 569 | if (ich_status_poll(SPIS_SCIP, 0) == -1) |
| 570 | return -1; |
| 571 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 572 | writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 573 | |
| 574 | spi_setup_type(&trans); |
| 575 | if ((opcode_index = spi_setup_opcode(&trans)) < 0) |
| 576 | return -1; |
| 577 | if ((with_address = spi_setup_offset(&trans)) < 0) |
| 578 | return -1; |
| 579 | |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 580 | if (trans.opcode == SPI_OPCODE_WREN) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 581 | /* |
| 582 | * Treat Write Enable as Atomic Pre-Op if possible |
| 583 | * in order to prevent the Management Engine from |
| 584 | * issuing a transaction between WREN and DATA. |
| 585 | */ |
Arthur Heymans | 816aaba | 2019-06-11 11:10:25 +0200 | [diff] [blame] | 586 | if (!spi_locked()) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 587 | writew_(trans.opcode, cntlr->preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 588 | return 0; |
| 589 | } |
| 590 | |
| 591 | /* Preset control fields */ |
| 592 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
| 593 | |
| 594 | /* Issue atomic preop cycle if needed */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 595 | if (readw_(cntlr->preop)) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 596 | control |= SPIC_ACS; |
| 597 | |
| 598 | if (!trans.bytesout && !trans.bytesin) { |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 599 | /* SPI addresses are 24 bit only */ |
| 600 | if (with_address) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 601 | writel_(trans.offset & 0x00FFFFFF, cntlr->addr); |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 602 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 603 | /* |
| 604 | * This is a 'no data' command (like Write Enable), its |
| 605 | * bitesout size was 1, decremented to zero while executing |
| 606 | * spi_setup_opcode() above. Tell the chip to send the |
| 607 | * command. |
| 608 | */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 609 | writew_(control, cntlr->control); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 610 | |
| 611 | /* wait for the result */ |
| 612 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 613 | if (status == -1) |
| 614 | return -1; |
| 615 | |
| 616 | if (status & SPIS_FCERR) { |
| 617 | printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); |
| 618 | return -1; |
| 619 | } |
| 620 | |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 621 | goto spi_xfer_exit; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 622 | } |
| 623 | |
| 624 | /* |
Paul Menzel | 9478297 | 2013-06-29 11:41:27 +0200 | [diff] [blame] | 625 | * Check if this is a write command attempting to transfer more bytes |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 626 | * than the controller can handle. Iterations for writes are not |
| 627 | * supported here because each SPI write command needs to be preceded |
| 628 | * and followed by other SPI commands, and this sequence is controlled |
| 629 | * by the SPI chip driver. |
| 630 | */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 631 | if (trans.bytesout > cntlr->databytes) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 632 | printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 633 | " spi_crop_chunk()?\n"); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 634 | return -1; |
| 635 | } |
| 636 | |
| 637 | /* |
| 638 | * Read or write up to databytes bytes at a time until everything has |
| 639 | * been sent. |
| 640 | */ |
| 641 | while (trans.bytesout || trans.bytesin) { |
| 642 | uint32_t data_length; |
| 643 | |
| 644 | /* SPI addresses are 24 bit only */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 645 | writel_(trans.offset & 0x00FFFFFF, cntlr->addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 646 | |
| 647 | if (trans.bytesout) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 648 | data_length = min(trans.bytesout, cntlr->databytes); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 649 | else |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 650 | data_length = min(trans.bytesin, cntlr->databytes); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 651 | |
| 652 | /* Program data into FDATA0 to N */ |
| 653 | if (trans.bytesout) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 654 | write_reg(trans.out, cntlr->data, data_length); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 655 | spi_use_out(&trans, data_length); |
| 656 | if (with_address) |
| 657 | trans.offset += data_length; |
| 658 | } |
| 659 | |
| 660 | /* Add proper control fields' values */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 661 | control &= ~((cntlr->databytes - 1) << 8); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 662 | control |= SPIC_DS; |
| 663 | control |= (data_length - 1) << 8; |
| 664 | |
| 665 | /* write it */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 666 | writew_(control, cntlr->control); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 667 | |
| 668 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
| 669 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 670 | if (status == -1) |
| 671 | return -1; |
| 672 | |
| 673 | if (status & SPIS_FCERR) { |
| 674 | printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); |
| 675 | return -1; |
| 676 | } |
| 677 | |
| 678 | if (trans.bytesin) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 679 | read_reg(cntlr->data, trans.in, data_length); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 680 | spi_use_in(&trans, data_length); |
| 681 | if (with_address) |
| 682 | trans.offset += data_length; |
| 683 | } |
| 684 | } |
| 685 | |
Werner Zeh | f13a6f9 | 2018-11-14 10:55:52 +0100 | [diff] [blame] | 686 | spi_xfer_exit: |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 687 | /* Clear atomic preop now that xfer is done */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 688 | writew_(0, cntlr->preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 689 | |
| 690 | return 0; |
| 691 | } |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 692 | |
| 693 | /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ |
| 694 | static void ich_hwseq_set_addr(uint32_t addr) |
| 695 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 696 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 697 | uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF; |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 698 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 699 | writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 700 | } |
| 701 | |
| 702 | /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. |
| 703 | Resets all error flags in HSFS. |
| 704 | Returns 0 if the cycle completes successfully without errors within |
| 705 | timeout us, 1 on errors. */ |
| 706 | static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, |
| 707 | unsigned int len) |
| 708 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 709 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 710 | uint16_t hsfs; |
| 711 | uint32_t addr; |
| 712 | |
| 713 | timeout /= 8; /* scale timeout duration to counter */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 714 | while ((((hsfs = readw_(&cntlr->ich9_spi->hsfs)) & |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 715 | (HSFS_FDONE | HSFS_FCERR)) == 0) && |
| 716 | --timeout) { |
| 717 | udelay(8); |
| 718 | } |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 719 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 720 | |
| 721 | if (!timeout) { |
| 722 | uint16_t hsfc; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 723 | addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; |
| 724 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 725 | printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " |
| 726 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 727 | addr, addr + len - 1, addr, len - 1, |
| 728 | hsfc, hsfs); |
| 729 | return 1; |
| 730 | } |
| 731 | |
| 732 | if (hsfs & HSFS_FCERR) { |
| 733 | uint16_t hsfc; |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 734 | addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; |
| 735 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 736 | printk(BIOS_ERR, "Transaction error between offset 0x%08x and " |
| 737 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 738 | addr, addr + len - 1, addr, len - 1, |
| 739 | hsfc, hsfs); |
| 740 | return 1; |
| 741 | } |
| 742 | return 0; |
| 743 | } |
| 744 | |
| 745 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 746 | static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, |
| 747 | size_t len) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 748 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 749 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 750 | u32 start, end, erase_size; |
| 751 | int ret; |
| 752 | uint16_t hsfc; |
Uwe Poeche | 17362be | 2019-07-17 14:27:13 +0200 | [diff] [blame] | 753 | unsigned int timeout = 1000 * SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 754 | |
| 755 | erase_size = flash->sector_size; |
| 756 | if (offset % erase_size || len % erase_size) { |
| 757 | printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); |
| 758 | return -1; |
| 759 | } |
| 760 | |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 761 | ret = spi_claim_bus(&flash->spi); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 762 | if (ret) { |
| 763 | printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); |
| 764 | return ret; |
| 765 | } |
| 766 | |
| 767 | start = offset; |
| 768 | end = start + len; |
| 769 | |
| 770 | while (offset < end) { |
| 771 | /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 772 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 773 | |
| 774 | ich_hwseq_set_addr(offset); |
| 775 | |
| 776 | offset += erase_size; |
| 777 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 778 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 779 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 780 | hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ |
| 781 | hsfc |= HSFC_FGO; /* start */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 782 | writew_(hsfc, &cntlr->ich9_spi->hsfc); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 783 | if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 784 | printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); |
| 785 | ret = -1; |
| 786 | goto out; |
| 787 | } |
| 788 | } |
| 789 | |
| 790 | printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); |
| 791 | |
| 792 | out: |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 793 | spi_release_bus(&flash->spi); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 794 | return ret; |
| 795 | } |
| 796 | |
| 797 | static void ich_read_data(uint8_t *data, int len) |
| 798 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 799 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 800 | int i; |
| 801 | uint32_t temp32 = 0; |
| 802 | |
| 803 | for (i = 0; i < len; i++) { |
| 804 | if ((i % 4) == 0) |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 805 | temp32 = readl_(cntlr->data + i); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 806 | |
| 807 | data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; |
| 808 | } |
| 809 | } |
| 810 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 811 | static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, |
| 812 | void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 813 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 814 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 815 | uint16_t hsfc; |
| 816 | uint16_t timeout = 100 * 60; |
| 817 | uint8_t block_len; |
| 818 | |
| 819 | if (addr + len > flash->size) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 820 | printk(BIOS_ERR, |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 821 | "Attempt to read %x-%x which is out of chip\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 822 | (unsigned int) addr, |
| 823 | (unsigned int) addr+(unsigned int) len); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 824 | return -1; |
| 825 | } |
| 826 | |
| 827 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 828 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 829 | |
| 830 | while (len > 0) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 831 | block_len = min(len, cntlr->databytes); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 832 | if (block_len > (~addr & 0xff)) |
| 833 | block_len = (~addr & 0xff) + 1; |
| 834 | ich_hwseq_set_addr(addr); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 835 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 836 | hsfc &= ~HSFC_FCYCLE; /* set read operation */ |
| 837 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 838 | /* set byte count */ |
| 839 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 840 | hsfc |= HSFC_FGO; /* start */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 841 | writew_(hsfc, &cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 842 | |
| 843 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) |
| 844 | return 1; |
| 845 | ich_read_data(buf, block_len); |
| 846 | addr += block_len; |
| 847 | buf += block_len; |
| 848 | len -= block_len; |
| 849 | } |
| 850 | return 0; |
| 851 | } |
| 852 | |
| 853 | /* Fill len bytes from the data array into the fdata/spid registers. |
| 854 | * |
| 855 | * Note that using len > flash->pgm->spi.max_data_write will trash the registers |
| 856 | * following the data registers. |
| 857 | */ |
| 858 | static void ich_fill_data(const uint8_t *data, int len) |
| 859 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 860 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 861 | uint32_t temp32 = 0; |
| 862 | int i; |
| 863 | |
| 864 | if (len <= 0) |
| 865 | return; |
| 866 | |
| 867 | for (i = 0; i < len; i++) { |
| 868 | if ((i % 4) == 0) |
| 869 | temp32 = 0; |
| 870 | |
| 871 | temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); |
| 872 | |
| 873 | if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 874 | writel_(temp32, cntlr->data + (i - (i % 4))); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 875 | } |
| 876 | i--; |
| 877 | if ((i % 4) != 3) /* Write remaining data to regs. */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 878 | writel_(temp32, cntlr->data + (i - (i % 4))); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 879 | } |
| 880 | |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 881 | static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, |
| 882 | const void *buf) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 883 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 884 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 885 | uint16_t hsfc; |
| 886 | uint16_t timeout = 100 * 60; |
| 887 | uint8_t block_len; |
| 888 | uint32_t start = addr; |
| 889 | |
| 890 | if (addr + len > flash->size) { |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 891 | printk(BIOS_ERR, |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 892 | "Attempt to write 0x%x-0x%x which is out of chip\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 893 | (unsigned int)addr, (unsigned int) (addr+len)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 894 | return -1; |
| 895 | } |
| 896 | |
| 897 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 898 | writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 899 | |
| 900 | while (len > 0) { |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 901 | block_len = min(len, cntlr->databytes); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 902 | if (block_len > (~addr & 0xff)) |
| 903 | block_len = (~addr & 0xff) + 1; |
| 904 | |
| 905 | ich_hwseq_set_addr(addr); |
| 906 | |
| 907 | ich_fill_data(buf, block_len); |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 908 | hsfc = readw_(&cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 909 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 910 | hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ |
| 911 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 912 | /* set byte count */ |
| 913 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 914 | hsfc |= HSFC_FGO; /* start */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 915 | writew_(hsfc, &cntlr->ich9_spi->hsfc); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 916 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 917 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { |
| 918 | printk(BIOS_ERR, "SF: write failure at %x\n", |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 919 | addr); |
| 920 | return -1; |
| 921 | } |
| 922 | addr += block_len; |
| 923 | buf += block_len; |
| 924 | len -= block_len; |
| 925 | } |
| 926 | printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 927 | (unsigned int) (addr - start), start); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 928 | return 0; |
| 929 | } |
| 930 | |
Furquan Shaikh | e2fc5e2 | 2017-05-17 17:26:01 -0700 | [diff] [blame] | 931 | static const struct spi_flash_ops spi_flash_ops = { |
| 932 | .read = ich_hwseq_read, |
| 933 | .write = ich_hwseq_write, |
| 934 | .erase = ich_hwseq_erase, |
| 935 | }; |
| 936 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 937 | static int spi_flash_programmer_probe(const struct spi_slave *spi, |
| 938 | struct spi_flash *flash) |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 939 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 940 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 941 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 942 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) |
Arthur Heymans | c88e370 | 2017-08-20 20:50:17 +0200 | [diff] [blame] | 943 | return spi_flash_generic_probe(spi, flash); |
| 944 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 945 | /* Try generic probing first if spi_is_multichip returns 0. */ |
| 946 | if (!spi_is_multichip() && !spi_flash_generic_probe(spi, flash)) |
| 947 | return 0; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 948 | |
Furquan Shaikh | 810e2cd | 2016-12-05 20:32:24 -0800 | [diff] [blame] | 949 | memcpy(&flash->spi, spi, sizeof(*spi)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 950 | flash->name = "Opaque HW-sequencing"; |
| 951 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 952 | ich_hwseq_set_addr(0); |
| 953 | switch ((cntlr->hsfs >> 3) & 3) { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 954 | case 0: |
| 955 | flash->sector_size = 256; |
| 956 | break; |
| 957 | case 1: |
| 958 | flash->sector_size = 4096; |
| 959 | break; |
| 960 | case 2: |
| 961 | flash->sector_size = 8192; |
| 962 | break; |
| 963 | case 3: |
| 964 | flash->sector_size = 65536; |
| 965 | break; |
| 966 | } |
| 967 | |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 968 | flash->size = 1 << (19 + (cntlr->flcomp & 7)); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 969 | |
Furquan Shaikh | e2fc5e2 | 2017-05-17 17:26:01 -0700 | [diff] [blame] | 970 | flash->ops = &spi_flash_ops; |
| 971 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 972 | if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3)) |
Stefan Tauner | 327205d | 2018-08-26 13:53:16 +0200 | [diff] [blame] | 973 | flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7)); |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 974 | printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 975 | |
Furquan Shaikh | 30221b4 | 2017-05-15 14:35:15 -0700 | [diff] [blame] | 976 | return 0; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 977 | } |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 978 | |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 979 | static int xfer_vectors(const struct spi_slave *slave, |
| 980 | struct spi_op vectors[], size_t count) |
| 981 | { |
| 982 | return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); |
| 983 | } |
| 984 | |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 985 | #define SPI_FPR_SHIFT 12 |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 986 | #define ICH7_SPI_FPR_MASK 0xfff |
| 987 | #define ICH9_SPI_FPR_MASK 0x1fff |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 988 | #define SPI_FPR_BASE_SHIFT 0 |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 989 | #define ICH7_SPI_FPR_LIMIT_SHIFT 12 |
| 990 | #define ICH9_SPI_FPR_LIMIT_SHIFT 16 |
| 991 | #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */ |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 992 | #define SPI_FPR_WPE (1 << 31) /* Write Protect */ |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 993 | |
| 994 | static u32 spi_fpr(u32 base, u32 limit) |
| 995 | { |
| 996 | u32 ret; |
| 997 | u32 mask, limit_shift; |
Elyes HAOUAS | ad19c2f | 2018-11-26 15:57:30 +0100 | [diff] [blame] | 998 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 999 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1000 | mask = ICH7_SPI_FPR_MASK; |
| 1001 | limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT; |
| 1002 | } else { |
| 1003 | mask = ICH9_SPI_FPR_MASK; |
| 1004 | limit_shift = ICH9_SPI_FPR_LIMIT_SHIFT; |
| 1005 | } |
| 1006 | ret = ((limit >> SPI_FPR_SHIFT) & mask) << limit_shift; |
| 1007 | ret |= ((base >> SPI_FPR_SHIFT) & mask) << SPI_FPR_BASE_SHIFT; |
| 1008 | return ret; |
| 1009 | } |
| 1010 | |
| 1011 | /* |
| 1012 | * Protect range of SPI flash defined by [start, start+size-1] using Flash |
| 1013 | * Protected Range (FPR) register if available. |
| 1014 | * Returns 0 on success, -1 on failure of programming fpr registers. |
| 1015 | */ |
| 1016 | static int spi_flash_protect(const struct spi_flash *flash, |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1017 | const struct region *region, |
| 1018 | const enum ctrlr_prot_type type) |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1019 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 1020 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1021 | u32 start = region_offset(region); |
| 1022 | u32 end = start + region_sz(region) - 1; |
| 1023 | u32 reg; |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1024 | u32 protect_mask = 0; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1025 | int fpr; |
| 1026 | uint32_t *fpr_base; |
| 1027 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 1028 | fpr_base = cntlr->fpr; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1029 | |
| 1030 | /* Find first empty FPR */ |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 1031 | for (fpr = 0; fpr < cntlr->fpr_max; fpr++) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1032 | reg = read32(&fpr_base[fpr]); |
| 1033 | if (reg == 0) |
| 1034 | break; |
| 1035 | } |
| 1036 | |
Arthur Heymans | 02c9971 | 2018-03-28 18:49:27 +0200 | [diff] [blame] | 1037 | if (fpr == cntlr->fpr_max) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1038 | printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); |
| 1039 | return -1; |
| 1040 | } |
| 1041 | |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1042 | switch (type) { |
| 1043 | case WRITE_PROTECT: |
| 1044 | protect_mask |= SPI_FPR_WPE; |
| 1045 | break; |
| 1046 | case READ_PROTECT: |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1047 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1048 | return -1; |
| 1049 | protect_mask |= ICH9_SPI_FPR_RPE; |
| 1050 | break; |
| 1051 | case READ_WRITE_PROTECT: |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1052 | if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1053 | return -1; |
| 1054 | protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE); |
| 1055 | break; |
| 1056 | default: |
| 1057 | printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n"); |
| 1058 | return -1; |
| 1059 | } |
| 1060 | |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1061 | /* Set protected range base and limit */ |
Rizwan Qureshi | f9f5093 | 2018-12-31 15:19:16 +0530 | [diff] [blame] | 1062 | reg = spi_fpr(start, end) | protect_mask; |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1063 | |
| 1064 | /* Set the FPR register and verify it is protected */ |
| 1065 | write32(&fpr_base[fpr], reg); |
Arthur Heymans | f957201 | 2019-06-11 11:15:10 +0200 | [diff] [blame] | 1066 | if (reg != read32(&fpr_base[fpr])) { |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1067 | printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr); |
| 1068 | return -1; |
| 1069 | } |
| 1070 | |
| 1071 | printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n", |
| 1072 | __func__, fpr, start, end); |
| 1073 | return 0; |
| 1074 | } |
| 1075 | |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1076 | void spi_finalize_ops(void) |
| 1077 | { |
Matt DeVillier | 4721e47 | 2019-05-18 16:05:00 -0500 | [diff] [blame] | 1078 | struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1079 | u16 spi_opprefix; |
| 1080 | u16 optype = 0; |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1081 | struct intel_swseq_spi_config spi_config_default = { |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1082 | {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1083 | { /* OPCODE and OPTYPE */ |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1084 | {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ |
| 1085 | {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ |
| 1086 | {0x03, READ_WITH_ADDR}, /* READ: Read Data */ |
| 1087 | {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ |
| 1088 | {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ |
| 1089 | {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ |
| 1090 | {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ |
| 1091 | {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */ |
| 1092 | } |
| 1093 | }; |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1094 | struct intel_swseq_spi_config spi_config_aai_write = { |
| 1095 | {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ |
| 1096 | { /* OPCODE and OPTYPE */ |
| 1097 | {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ |
| 1098 | {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ |
| 1099 | {0x03, READ_WITH_ADDR}, /* READ: Read Data */ |
| 1100 | {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ |
| 1101 | {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ |
| 1102 | {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ |
| 1103 | {0xad, WRITE_NO_ADDR}, /* Auto Address Increment Word Program */ |
| 1104 | {0x04, WRITE_NO_ADDR} /* Write Disable */ |
| 1105 | } |
| 1106 | }; |
| 1107 | const struct spi_flash *flash = boot_device_spi_flash(); |
| 1108 | struct intel_swseq_spi_config *spi_config = &spi_config_default; |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1109 | int i; |
| 1110 | |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1111 | /* |
| 1112 | * Some older SST SPI flashes support AAI write but use 0xaf opcde for |
| 1113 | * that. Flashrom uses the byte program opcode to write those flashes, |
| 1114 | * so this configuration is fine too. SST25VF064C (id = 0x4b) is an |
| 1115 | * exception. |
| 1116 | */ |
| 1117 | if (flash && flash->vendor == VENDOR_ID_SST && (flash->model & 0x00ff) != 0x4b) |
| 1118 | spi_config = &spi_config_aai_write; |
| 1119 | |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1120 | if (spi_locked()) |
| 1121 | return; |
| 1122 | |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1123 | intel_southbridge_override_spi(spi_config); |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1124 | |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1125 | spi_opprefix = spi_config->opprefixes[0] |
| 1126 | | (spi_config->opprefixes[1] << 8); |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1127 | writew_(spi_opprefix, cntlr->preop); |
Arthur Heymans | 50b4f78 | 2019-09-23 11:49:17 +0200 | [diff] [blame] | 1128 | for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) { |
| 1129 | optype |= (spi_config->ops[i].type & 3) << (i * 2); |
| 1130 | writeb_(spi_config->ops[i].op, &cntlr->opmenu[i]); |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1131 | } |
Nico Huber | eaeb0b7 | 2019-07-27 13:45:58 +0200 | [diff] [blame] | 1132 | writew_(optype, cntlr->optype); |
Arthur Heymans | 92185e3 | 2019-05-28 13:06:34 +0200 | [diff] [blame] | 1133 | } |
| 1134 | |
| 1135 | __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) |
| 1136 | { |
| 1137 | } |
| 1138 | |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1139 | static const struct spi_ctrlr spi_ctrlr = { |
Aaron Durbin | 851dde8 | 2018-04-19 21:15:25 -0600 | [diff] [blame] | 1140 | .xfer_vector = xfer_vectors, |
Arthur Heymans | a9c1a5f | 2019-06-15 18:21:58 +0200 | [diff] [blame] | 1141 | .max_xfer_size = member_size(struct ich9_spi_regs, fdata), |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1142 | .flash_probe = spi_flash_programmer_probe, |
Arthur Heymans | 11fcb2bc | 2018-01-07 20:46:31 +0100 | [diff] [blame] | 1143 | .flash_protect = spi_flash_protect, |
Furquan Shaikh | a149157 | 2017-05-17 19:14:06 -0700 | [diff] [blame] | 1144 | }; |
| 1145 | |
Furquan Shaikh | 2cd03f1 | 2017-05-18 14:58:32 -0700 | [diff] [blame] | 1146 | const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { |
| 1147 | { |
| 1148 | .ctrlr = &spi_ctrlr, |
| 1149 | .bus_start = 0, |
| 1150 | .bus_end = 0, |
| 1151 | }, |
| 1152 | }; |
| 1153 | |
| 1154 | const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); |