Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 3 | * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger |
| 4 | * Copyright (C) 2011 Stefan Tauner |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but without any warranty; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | /* This file is derived from the flashrom project. */ |
| 26 | #include <stdint.h> |
| 27 | #include <stdlib.h> |
| 28 | #include <string.h> |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame^] | 29 | #include <bootstate.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 30 | #include <delay.h> |
| 31 | #include <arch/io.h> |
| 32 | #include <console/console.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 33 | #include <device/pci_ids.h> |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 34 | #include <device/pci.h> |
| 35 | #include <spi_flash.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 36 | |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 37 | #include <spi-generic.h> |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 38 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 39 | #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ |
| 40 | #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) |
| 41 | #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ |
| 42 | #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) |
| 43 | |
| 44 | |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 45 | #ifdef __SMM__ |
Kyösti Mälkki | 54d6abd | 2013-06-19 23:05:00 +0300 | [diff] [blame] | 46 | #include <arch/pci_mmio_cfg.h> |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 47 | #define pci_read_config_byte(dev, reg, targ)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 48 | *(targ) = pci_read_config8(dev, reg) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 49 | #define pci_read_config_word(dev, reg, targ)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 50 | *(targ) = pci_read_config16(dev, reg) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 51 | #define pci_read_config_dword(dev, reg, targ)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 52 | *(targ) = pci_read_config32(dev, reg) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 53 | #define pci_write_config_byte(dev, reg, val)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 54 | pci_write_config8(dev, reg, val) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 55 | #define pci_write_config_word(dev, reg, val)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 56 | pci_write_config16(dev, reg, val) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 57 | #define pci_write_config_dword(dev, reg, val)\ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 58 | pci_write_config32(dev, reg, val) |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 59 | #else /* !__SMM__ */ |
| 60 | #include <device/device.h> |
| 61 | #include <device/pci.h> |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 62 | #define pci_read_config_byte(dev, reg, targ)\ |
| 63 | *(targ) = pci_read_config8(dev, reg) |
| 64 | #define pci_read_config_word(dev, reg, targ)\ |
| 65 | *(targ) = pci_read_config16(dev, reg) |
| 66 | #define pci_read_config_dword(dev, reg, targ)\ |
| 67 | *(targ) = pci_read_config32(dev, reg) |
| 68 | #define pci_write_config_byte(dev, reg, val)\ |
| 69 | pci_write_config8(dev, reg, val) |
| 70 | #define pci_write_config_word(dev, reg, val)\ |
| 71 | pci_write_config16(dev, reg, val) |
| 72 | #define pci_write_config_dword(dev, reg, val)\ |
| 73 | pci_write_config32(dev, reg, val) |
| 74 | #endif /* !__SMM__ */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 75 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 76 | static int spi_is_multichip(void); |
| 77 | static struct spi_flash *spi_flash_hwseq(struct spi_slave *spi); |
| 78 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 79 | typedef struct spi_slave ich_spi_slave; |
| 80 | |
| 81 | static int ichspi_lock = 0; |
| 82 | |
| 83 | typedef struct ich7_spi_regs { |
| 84 | uint16_t spis; |
| 85 | uint16_t spic; |
| 86 | uint32_t spia; |
| 87 | uint64_t spid[8]; |
| 88 | uint64_t _pad; |
| 89 | uint32_t bbar; |
| 90 | uint16_t preop; |
| 91 | uint16_t optype; |
| 92 | uint8_t opmenu[8]; |
| 93 | } __attribute__((packed)) ich7_spi_regs; |
| 94 | |
| 95 | typedef struct ich9_spi_regs { |
| 96 | uint32_t bfpr; |
| 97 | uint16_t hsfs; |
| 98 | uint16_t hsfc; |
| 99 | uint32_t faddr; |
| 100 | uint32_t _reserved0; |
| 101 | uint32_t fdata[16]; |
| 102 | uint32_t frap; |
| 103 | uint32_t freg[5]; |
| 104 | uint32_t _reserved1[3]; |
| 105 | uint32_t pr[5]; |
| 106 | uint32_t _reserved2[2]; |
| 107 | uint8_t ssfs; |
| 108 | uint8_t ssfc[3]; |
| 109 | uint16_t preop; |
| 110 | uint16_t optype; |
| 111 | uint8_t opmenu[8]; |
| 112 | uint32_t bbar; |
| 113 | uint8_t _reserved3[12]; |
| 114 | uint32_t fdoc; |
| 115 | uint32_t fdod; |
| 116 | uint8_t _reserved4[8]; |
| 117 | uint32_t afc; |
| 118 | uint32_t lvscc; |
| 119 | uint32_t uvscc; |
| 120 | uint8_t _reserved5[4]; |
| 121 | uint32_t fpb; |
| 122 | uint8_t _reserved6[28]; |
| 123 | uint32_t srdl; |
| 124 | uint32_t srdc; |
| 125 | uint32_t srd; |
| 126 | } __attribute__((packed)) ich9_spi_regs; |
| 127 | |
| 128 | typedef struct ich_spi_controller { |
| 129 | int locked; |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 130 | uint32_t flmap0; |
| 131 | uint32_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 132 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 133 | ich9_spi_regs *ich9_spi; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 134 | uint8_t *opmenu; |
| 135 | int menubytes; |
| 136 | uint16_t *preop; |
| 137 | uint16_t *optype; |
| 138 | uint32_t *addr; |
| 139 | uint8_t *data; |
| 140 | unsigned databytes; |
| 141 | uint8_t *status; |
| 142 | uint16_t *control; |
| 143 | uint32_t *bbar; |
| 144 | } ich_spi_controller; |
| 145 | |
| 146 | static ich_spi_controller cntlr; |
| 147 | |
| 148 | enum { |
| 149 | SPIS_SCIP = 0x0001, |
| 150 | SPIS_GRANT = 0x0002, |
| 151 | SPIS_CDS = 0x0004, |
| 152 | SPIS_FCERR = 0x0008, |
| 153 | SSFS_AEL = 0x0010, |
| 154 | SPIS_LOCK = 0x8000, |
| 155 | SPIS_RESERVED_MASK = 0x7ff0, |
| 156 | SSFS_RESERVED_MASK = 0x7fe2 |
| 157 | }; |
| 158 | |
| 159 | enum { |
| 160 | SPIC_SCGO = 0x000002, |
| 161 | SPIC_ACS = 0x000004, |
| 162 | SPIC_SPOP = 0x000008, |
| 163 | SPIC_DBC = 0x003f00, |
| 164 | SPIC_DS = 0x004000, |
| 165 | SPIC_SME = 0x008000, |
| 166 | SSFC_SCF_MASK = 0x070000, |
| 167 | SSFC_RESERVED = 0xf80000 |
| 168 | }; |
| 169 | |
| 170 | enum { |
| 171 | HSFS_FDONE = 0x0001, |
| 172 | HSFS_FCERR = 0x0002, |
| 173 | HSFS_AEL = 0x0004, |
| 174 | HSFS_BERASE_MASK = 0x0018, |
| 175 | HSFS_BERASE_SHIFT = 3, |
| 176 | HSFS_SCIP = 0x0020, |
| 177 | HSFS_FDOPSS = 0x2000, |
| 178 | HSFS_FDV = 0x4000, |
| 179 | HSFS_FLOCKDN = 0x8000 |
| 180 | }; |
| 181 | |
| 182 | enum { |
| 183 | HSFC_FGO = 0x0001, |
| 184 | HSFC_FCYCLE_MASK = 0x0006, |
| 185 | HSFC_FCYCLE_SHIFT = 1, |
| 186 | HSFC_FDBC_MASK = 0x3f00, |
| 187 | HSFC_FDBC_SHIFT = 8, |
| 188 | HSFC_FSMIE = 0x8000 |
| 189 | }; |
| 190 | |
| 191 | enum { |
| 192 | SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| 193 | SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| 194 | SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| 195 | SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| 196 | }; |
| 197 | |
| 198 | #if CONFIG_DEBUG_SPI_FLASH |
| 199 | |
| 200 | static u8 readb_(const void *addr) |
| 201 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 202 | u8 v = read8((unsigned long)addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 203 | printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", |
| 204 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 205 | return v; |
| 206 | } |
| 207 | |
| 208 | static u16 readw_(const void *addr) |
| 209 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 210 | u16 v = read16((unsigned long)addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 211 | printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", |
| 212 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 213 | return v; |
| 214 | } |
| 215 | |
| 216 | static u32 readl_(const void *addr) |
| 217 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 218 | u32 v = read32((unsigned long)addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 219 | printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", |
| 220 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 221 | return v; |
| 222 | } |
| 223 | |
| 224 | static void writeb_(u8 b, const void *addr) |
| 225 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 226 | write8((unsigned long)addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 227 | printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", |
| 228 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 229 | } |
| 230 | |
| 231 | static void writew_(u16 b, const void *addr) |
| 232 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 233 | write16((unsigned long)addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 234 | printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", |
| 235 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 236 | } |
| 237 | |
| 238 | static void writel_(u32 b, const void *addr) |
| 239 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 240 | write32((unsigned long)addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 241 | printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", |
| 242 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 243 | } |
| 244 | |
| 245 | #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ |
| 246 | |
| 247 | #define readb_(a) read8((uint32_t)a) |
| 248 | #define readw_(a) read16((uint32_t)a) |
| 249 | #define readl_(a) read32((uint32_t)a) |
| 250 | #define writeb_(val, addr) write8((uint32_t)addr, val) |
| 251 | #define writew_(val, addr) write16((uint32_t)addr, val) |
| 252 | #define writel_(val, addr) write32((uint32_t)addr, val) |
| 253 | |
| 254 | #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ |
| 255 | |
| 256 | static void write_reg(const void *value, void *dest, uint32_t size) |
| 257 | { |
| 258 | const uint8_t *bvalue = value; |
| 259 | uint8_t *bdest = dest; |
| 260 | |
| 261 | while (size >= 4) { |
| 262 | writel_(*(const uint32_t *)bvalue, bdest); |
| 263 | bdest += 4; bvalue += 4; size -= 4; |
| 264 | } |
| 265 | while (size) { |
| 266 | writeb_(*bvalue, bdest); |
| 267 | bdest++; bvalue++; size--; |
| 268 | } |
| 269 | } |
| 270 | |
| 271 | static void read_reg(const void *src, void *value, uint32_t size) |
| 272 | { |
| 273 | const uint8_t *bsrc = src; |
| 274 | uint8_t *bvalue = value; |
| 275 | |
| 276 | while (size >= 4) { |
| 277 | *(uint32_t *)bvalue = readl_(bsrc); |
| 278 | bsrc += 4; bvalue += 4; size -= 4; |
| 279 | } |
| 280 | while (size) { |
| 281 | *bvalue = readb_(bsrc); |
| 282 | bsrc++; bvalue++; size--; |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | static void ich_set_bbar(uint32_t minaddr) |
| 287 | { |
| 288 | const uint32_t bbar_mask = 0x00ffff00; |
| 289 | uint32_t ichspi_bbar; |
| 290 | |
| 291 | minaddr &= bbar_mask; |
| 292 | ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; |
| 293 | ichspi_bbar |= minaddr; |
| 294 | writel_(ichspi_bbar, cntlr.bbar); |
| 295 | } |
| 296 | |
Gabe Black | 1e18735 | 2014-03-27 20:37:03 -0700 | [diff] [blame] | 297 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 298 | { |
| 299 | ich_spi_slave *slave = malloc(sizeof(*slave)); |
| 300 | |
| 301 | if (!slave) { |
| 302 | printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); |
| 303 | return NULL; |
| 304 | } |
| 305 | |
| 306 | memset(slave, 0, sizeof(*slave)); |
| 307 | |
| 308 | slave->bus = bus; |
| 309 | slave->cs = cs; |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 310 | slave->force_programmer_specific = spi_is_multichip (); |
| 311 | slave->programmer_specific_probe = spi_flash_hwseq; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 312 | return slave; |
| 313 | } |
| 314 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 315 | void spi_init(void) |
| 316 | { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 317 | uint8_t *rcrb; /* Root Complex Register Block */ |
| 318 | uint32_t rcba; /* Root Complex Base Address */ |
| 319 | uint8_t bios_cntl; |
Stefan Reinauer | 0c32c97 | 2012-07-10 13:26:59 -0700 | [diff] [blame] | 320 | device_t dev; |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 321 | ich9_spi_regs *ich9_spi; |
| 322 | uint16_t hsfs; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 323 | |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 324 | #ifdef __SMM__ |
| 325 | dev = PCI_DEV(0, 31, 0); |
| 326 | #else |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 327 | dev = dev_find_slot(0, PCI_DEVFN(31, 0)); |
Duncan Laurie | 181bbdd | 2012-06-23 16:53:57 -0700 | [diff] [blame] | 328 | #endif |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 329 | |
| 330 | pci_read_config_dword(dev, 0xf0, &rcba); |
| 331 | /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ |
| 332 | rcrb = (uint8_t *)(rcba & 0xffffc000); |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 333 | ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); |
| 334 | cntlr.ich9_spi = ich9_spi; |
| 335 | hsfs = readw_(&ich9_spi->hsfs); |
| 336 | ichspi_lock = hsfs & HSFS_FLOCKDN; |
| 337 | cntlr.hsfs = hsfs; |
| 338 | cntlr.opmenu = ich9_spi->opmenu; |
| 339 | cntlr.menubytes = sizeof(ich9_spi->opmenu); |
| 340 | cntlr.optype = &ich9_spi->optype; |
| 341 | cntlr.addr = &ich9_spi->faddr; |
| 342 | cntlr.data = (uint8_t *)ich9_spi->fdata; |
| 343 | cntlr.databytes = sizeof(ich9_spi->fdata); |
| 344 | cntlr.status = &ich9_spi->ssfs; |
| 345 | cntlr.control = (uint16_t *)ich9_spi->ssfc; |
| 346 | cntlr.bbar = &ich9_spi->bbar; |
| 347 | cntlr.preop = &ich9_spi->preop; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 348 | |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 349 | if (cntlr.hsfs & HSFS_FDV) |
| 350 | { |
| 351 | writel_ (4, &ich9_spi->fdoc); |
| 352 | cntlr.flmap0 = readl_(&ich9_spi->fdod); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 353 | } |
| 354 | |
| 355 | ich_set_bbar(0); |
| 356 | |
| 357 | /* Disable the BIOS write protect so write commands are allowed. */ |
| 358 | pci_read_config_byte(dev, 0xdc, &bios_cntl); |
Vladimir Serbinenko | 42c4a9d | 2014-02-16 17:13:19 +0100 | [diff] [blame] | 359 | /* Deassert SMM BIOS Write Protect Disable. */ |
| 360 | bios_cntl &= ~(1 << 5); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 361 | pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); |
| 362 | } |
David Hendricks | f2612a1 | 2014-04-13 16:27:02 -0700 | [diff] [blame^] | 363 | static void spi_init_cb(void *unused) |
| 364 | { |
| 365 | spi_init(); |
| 366 | } |
| 367 | |
| 368 | BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { |
| 369 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), |
| 370 | }; |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 371 | |
| 372 | int spi_claim_bus(struct spi_slave *slave) |
| 373 | { |
| 374 | /* Handled by ICH automatically. */ |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | void spi_release_bus(struct spi_slave *slave) |
| 379 | { |
| 380 | /* Handled by ICH automatically. */ |
| 381 | } |
| 382 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 383 | typedef struct spi_transaction { |
| 384 | const uint8_t *out; |
| 385 | uint32_t bytesout; |
| 386 | uint8_t *in; |
| 387 | uint32_t bytesin; |
| 388 | uint8_t type; |
| 389 | uint8_t opcode; |
| 390 | uint32_t offset; |
| 391 | } spi_transaction; |
| 392 | |
| 393 | static inline void spi_use_out(spi_transaction *trans, unsigned bytes) |
| 394 | { |
| 395 | trans->out += bytes; |
| 396 | trans->bytesout -= bytes; |
| 397 | } |
| 398 | |
| 399 | static inline void spi_use_in(spi_transaction *trans, unsigned bytes) |
| 400 | { |
| 401 | trans->in += bytes; |
| 402 | trans->bytesin -= bytes; |
| 403 | } |
| 404 | |
| 405 | static void spi_setup_type(spi_transaction *trans) |
| 406 | { |
| 407 | trans->type = 0xFF; |
| 408 | |
| 409 | /* Try to guess spi type from read/write sizes. */ |
| 410 | if (trans->bytesin == 0) { |
| 411 | if (trans->bytesout > 4) |
| 412 | /* |
| 413 | * If bytesin = 0 and bytesout > 4, we presume this is |
| 414 | * a write data operation, which is accompanied by an |
| 415 | * address. |
| 416 | */ |
| 417 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
| 418 | else |
| 419 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 420 | return; |
| 421 | } |
| 422 | |
| 423 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
| 424 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 425 | return; |
| 426 | } |
| 427 | |
| 428 | if (trans->bytesout == 4) { /* and bytesin is > 0 */ |
| 429 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 430 | } |
Duncan Laurie | 23b0053 | 2012-10-10 14:21:23 -0700 | [diff] [blame] | 431 | |
| 432 | /* Fast read command is called with 5 bytes instead of 4 */ |
| 433 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { |
| 434 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 435 | --trans->bytesout; |
| 436 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | static int spi_setup_opcode(spi_transaction *trans) |
| 440 | { |
| 441 | uint16_t optypes; |
| 442 | uint8_t opmenu[cntlr.menubytes]; |
| 443 | |
| 444 | trans->opcode = trans->out[0]; |
| 445 | spi_use_out(trans, 1); |
| 446 | if (!ichspi_lock) { |
| 447 | /* The lock is off, so just use index 0. */ |
| 448 | writeb_(trans->opcode, cntlr.opmenu); |
| 449 | optypes = readw_(cntlr.optype); |
| 450 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
| 451 | writew_(optypes, cntlr.optype); |
| 452 | return 0; |
| 453 | } else { |
| 454 | /* The lock is on. See if what we need is on the menu. */ |
| 455 | uint8_t optype; |
| 456 | uint16_t opcode_index; |
| 457 | |
Duncan Laurie | a2f1b95 | 2012-08-27 11:10:43 -0700 | [diff] [blame] | 458 | /* Write Enable is handled as atomic prefix */ |
| 459 | if (trans->opcode == SPI_OPCODE_WREN) |
| 460 | return 0; |
| 461 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 462 | read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); |
| 463 | for (opcode_index = 0; opcode_index < cntlr.menubytes; |
| 464 | opcode_index++) { |
| 465 | if (opmenu[opcode_index] == trans->opcode) |
| 466 | break; |
| 467 | } |
| 468 | |
| 469 | if (opcode_index == cntlr.menubytes) { |
| 470 | printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", |
| 471 | trans->opcode); |
| 472 | return -1; |
| 473 | } |
| 474 | |
| 475 | optypes = readw_(cntlr.optype); |
| 476 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
| 477 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
| 478 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
| 479 | trans->bytesout >= 3) { |
| 480 | /* We guessed wrong earlier. Fix it up. */ |
| 481 | trans->type = optype; |
| 482 | } |
| 483 | if (optype != trans->type) { |
| 484 | printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", |
| 485 | optype); |
| 486 | return -1; |
| 487 | } |
| 488 | return opcode_index; |
| 489 | } |
| 490 | } |
| 491 | |
| 492 | static int spi_setup_offset(spi_transaction *trans) |
| 493 | { |
| 494 | /* Separate the SPI address and data. */ |
| 495 | switch (trans->type) { |
| 496 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
| 497 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
| 498 | return 0; |
| 499 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
| 500 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
| 501 | trans->offset = ((uint32_t)trans->out[0] << 16) | |
| 502 | ((uint32_t)trans->out[1] << 8) | |
| 503 | ((uint32_t)trans->out[2] << 0); |
| 504 | spi_use_out(trans, 3); |
| 505 | return 1; |
| 506 | default: |
| 507 | printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); |
| 508 | return -1; |
| 509 | } |
| 510 | } |
| 511 | |
| 512 | /* |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 513 | * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 514 | * below is True) or 0. In case the wait was for the bit(s) to set - write |
| 515 | * those bits back, which would cause resetting them. |
| 516 | * |
| 517 | * Return the last read status value on success or -1 on failure. |
| 518 | */ |
| 519 | static int ich_status_poll(u16 bitmask, int wait_til_set) |
| 520 | { |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 521 | int timeout = 600000; /* This will result in 6 seconds */ |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 522 | u16 status = 0; |
| 523 | |
| 524 | while (timeout--) { |
| 525 | status = readw_(cntlr.status); |
| 526 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
| 527 | if (wait_til_set) |
| 528 | writew_((status & bitmask), cntlr.status); |
| 529 | return status; |
| 530 | } |
| 531 | udelay(10); |
| 532 | } |
| 533 | |
Philipp Deppenwiese | 93643e3 | 2014-10-17 16:10:32 +0200 | [diff] [blame] | 534 | printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n", |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 535 | status, bitmask); |
| 536 | return -1; |
| 537 | } |
| 538 | |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 539 | static int spi_is_multichip (void) |
| 540 | { |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 541 | if (!(cntlr.hsfs & HSFS_FDV)) |
| 542 | return 0; |
| 543 | return !!((cntlr.flmap0 >> 8) & 3); |
| 544 | } |
| 545 | |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 546 | unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) |
| 547 | { |
| 548 | return min(cntlr.databytes, buf_len); |
| 549 | } |
| 550 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 551 | int spi_xfer(struct spi_slave *slave, const void *dout, |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 552 | unsigned int bytesout, void *din, unsigned int bytesin) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 553 | { |
| 554 | uint16_t control; |
| 555 | int16_t opcode_index; |
| 556 | int with_address; |
| 557 | int status; |
| 558 | |
| 559 | spi_transaction trans = { |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 560 | dout, bytesout, |
| 561 | din, bytesin, |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 562 | 0xff, 0xff, 0 |
| 563 | }; |
| 564 | |
| 565 | /* There has to always at least be an opcode. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 566 | if (!bytesout || !dout) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 567 | printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); |
| 568 | return -1; |
| 569 | } |
| 570 | /* Make sure if we read something we have a place to put it. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 571 | if (bytesin != 0 && !din) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 572 | printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); |
| 573 | return -1; |
| 574 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 575 | |
| 576 | if (ich_status_poll(SPIS_SCIP, 0) == -1) |
| 577 | return -1; |
| 578 | |
| 579 | writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); |
| 580 | |
| 581 | spi_setup_type(&trans); |
| 582 | if ((opcode_index = spi_setup_opcode(&trans)) < 0) |
| 583 | return -1; |
| 584 | if ((with_address = spi_setup_offset(&trans)) < 0) |
| 585 | return -1; |
| 586 | |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 587 | if (trans.opcode == SPI_OPCODE_WREN) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 588 | /* |
| 589 | * Treat Write Enable as Atomic Pre-Op if possible |
| 590 | * in order to prevent the Management Engine from |
| 591 | * issuing a transaction between WREN and DATA. |
| 592 | */ |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 593 | if (!ichspi_lock) |
| 594 | writew_(trans.opcode, cntlr.preop); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 595 | return 0; |
| 596 | } |
| 597 | |
| 598 | /* Preset control fields */ |
| 599 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
| 600 | |
| 601 | /* Issue atomic preop cycle if needed */ |
| 602 | if (readw_(cntlr.preop)) |
| 603 | control |= SPIC_ACS; |
| 604 | |
| 605 | if (!trans.bytesout && !trans.bytesin) { |
Duncan Laurie | 3beb6db | 2012-09-01 13:44:17 -0700 | [diff] [blame] | 606 | /* SPI addresses are 24 bit only */ |
| 607 | if (with_address) |
| 608 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
| 609 | |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 610 | /* |
| 611 | * This is a 'no data' command (like Write Enable), its |
| 612 | * bitesout size was 1, decremented to zero while executing |
| 613 | * spi_setup_opcode() above. Tell the chip to send the |
| 614 | * command. |
| 615 | */ |
| 616 | writew_(control, cntlr.control); |
| 617 | |
| 618 | /* wait for the result */ |
| 619 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 620 | if (status == -1) |
| 621 | return -1; |
| 622 | |
| 623 | if (status & SPIS_FCERR) { |
| 624 | printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); |
| 625 | return -1; |
| 626 | } |
| 627 | |
| 628 | return 0; |
| 629 | } |
| 630 | |
| 631 | /* |
Paul Menzel | 9478297 | 2013-06-29 11:41:27 +0200 | [diff] [blame] | 632 | * Check if this is a write command attempting to transfer more bytes |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 633 | * than the controller can handle. Iterations for writes are not |
| 634 | * supported here because each SPI write command needs to be preceded |
| 635 | * and followed by other SPI commands, and this sequence is controlled |
| 636 | * by the SPI chip driver. |
| 637 | */ |
| 638 | if (trans.bytesout > cntlr.databytes) { |
| 639 | printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 640 | " spi_crop_chunk()?\n"); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 641 | return -1; |
| 642 | } |
| 643 | |
| 644 | /* |
| 645 | * Read or write up to databytes bytes at a time until everything has |
| 646 | * been sent. |
| 647 | */ |
| 648 | while (trans.bytesout || trans.bytesin) { |
| 649 | uint32_t data_length; |
| 650 | |
| 651 | /* SPI addresses are 24 bit only */ |
| 652 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
| 653 | |
| 654 | if (trans.bytesout) |
| 655 | data_length = min(trans.bytesout, cntlr.databytes); |
| 656 | else |
| 657 | data_length = min(trans.bytesin, cntlr.databytes); |
| 658 | |
| 659 | /* Program data into FDATA0 to N */ |
| 660 | if (trans.bytesout) { |
| 661 | write_reg(trans.out, cntlr.data, data_length); |
| 662 | spi_use_out(&trans, data_length); |
| 663 | if (with_address) |
| 664 | trans.offset += data_length; |
| 665 | } |
| 666 | |
| 667 | /* Add proper control fields' values */ |
| 668 | control &= ~((cntlr.databytes - 1) << 8); |
| 669 | control |= SPIC_DS; |
| 670 | control |= (data_length - 1) << 8; |
| 671 | |
| 672 | /* write it */ |
| 673 | writew_(control, cntlr.control); |
| 674 | |
| 675 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
| 676 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 677 | if (status == -1) |
| 678 | return -1; |
| 679 | |
| 680 | if (status & SPIS_FCERR) { |
| 681 | printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); |
| 682 | return -1; |
| 683 | } |
| 684 | |
| 685 | if (trans.bytesin) { |
| 686 | read_reg(cntlr.data, trans.in, data_length); |
| 687 | spi_use_in(&trans, data_length); |
| 688 | if (with_address) |
| 689 | trans.offset += data_length; |
| 690 | } |
| 691 | } |
| 692 | |
| 693 | /* Clear atomic preop now that xfer is done */ |
| 694 | writew_(0, cntlr.preop); |
| 695 | |
| 696 | return 0; |
| 697 | } |
Vladimir Serbinenko | f3c7a9c | 2014-01-04 21:00:38 +0100 | [diff] [blame] | 698 | |
| 699 | /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ |
| 700 | static void ich_hwseq_set_addr(uint32_t addr) |
| 701 | { |
| 702 | uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; |
| 703 | writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); |
| 704 | } |
| 705 | |
| 706 | /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. |
| 707 | Resets all error flags in HSFS. |
| 708 | Returns 0 if the cycle completes successfully without errors within |
| 709 | timeout us, 1 on errors. */ |
| 710 | static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, |
| 711 | unsigned int len) |
| 712 | { |
| 713 | uint16_t hsfs; |
| 714 | uint32_t addr; |
| 715 | |
| 716 | timeout /= 8; /* scale timeout duration to counter */ |
| 717 | while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & |
| 718 | (HSFS_FDONE | HSFS_FCERR)) == 0) && |
| 719 | --timeout) { |
| 720 | udelay(8); |
| 721 | } |
| 722 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
| 723 | |
| 724 | if (!timeout) { |
| 725 | uint16_t hsfc; |
| 726 | addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; |
| 727 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 728 | printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " |
| 729 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 730 | addr, addr + len - 1, addr, len - 1, |
| 731 | hsfc, hsfs); |
| 732 | return 1; |
| 733 | } |
| 734 | |
| 735 | if (hsfs & HSFS_FCERR) { |
| 736 | uint16_t hsfc; |
| 737 | addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; |
| 738 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 739 | printk(BIOS_ERR, "Transaction error between offset 0x%08x and " |
| 740 | "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", |
| 741 | addr, addr + len - 1, addr, len - 1, |
| 742 | hsfc, hsfs); |
| 743 | return 1; |
| 744 | } |
| 745 | return 0; |
| 746 | } |
| 747 | |
| 748 | |
| 749 | static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) |
| 750 | { |
| 751 | u32 start, end, erase_size; |
| 752 | int ret; |
| 753 | uint16_t hsfc; |
| 754 | uint16_t timeout = 1000 * 60; |
| 755 | |
| 756 | erase_size = flash->sector_size; |
| 757 | if (offset % erase_size || len % erase_size) { |
| 758 | printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); |
| 759 | return -1; |
| 760 | } |
| 761 | |
| 762 | flash->spi->rw = SPI_WRITE_FLAG; |
| 763 | ret = spi_claim_bus(flash->spi); |
| 764 | if (ret) { |
| 765 | printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); |
| 766 | return ret; |
| 767 | } |
| 768 | |
| 769 | start = offset; |
| 770 | end = start + len; |
| 771 | |
| 772 | while (offset < end) { |
| 773 | /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ |
| 774 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
| 775 | |
| 776 | ich_hwseq_set_addr(offset); |
| 777 | |
| 778 | offset += erase_size; |
| 779 | |
| 780 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 781 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 782 | hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ |
| 783 | hsfc |= HSFC_FGO; /* start */ |
| 784 | writew_(hsfc, &cntlr.ich9_spi->hsfc); |
| 785 | if (ich_hwseq_wait_for_cycle_complete(timeout, len)) |
| 786 | { |
| 787 | printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); |
| 788 | ret = -1; |
| 789 | goto out; |
| 790 | } |
| 791 | } |
| 792 | |
| 793 | printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); |
| 794 | |
| 795 | out: |
| 796 | spi_release_bus(flash->spi); |
| 797 | return ret; |
| 798 | } |
| 799 | |
| 800 | static void ich_read_data(uint8_t *data, int len) |
| 801 | { |
| 802 | int i; |
| 803 | uint32_t temp32 = 0; |
| 804 | |
| 805 | for (i = 0; i < len; i++) { |
| 806 | if ((i % 4) == 0) |
| 807 | temp32 = readl_(cntlr.data + i); |
| 808 | |
| 809 | data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; |
| 810 | } |
| 811 | } |
| 812 | |
| 813 | static int ich_hwseq_read(struct spi_flash *flash, |
| 814 | u32 addr, size_t len, void *buf) |
| 815 | { |
| 816 | uint16_t hsfc; |
| 817 | uint16_t timeout = 100 * 60; |
| 818 | uint8_t block_len; |
| 819 | |
| 820 | if (addr + len > flash->size) { |
| 821 | printk (BIOS_ERR, |
| 822 | "Attempt to read %x-%x which is out of chip\n", |
| 823 | (unsigned) addr, |
| 824 | (unsigned) addr+(unsigned) len); |
| 825 | return -1; |
| 826 | } |
| 827 | |
| 828 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
| 829 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
| 830 | |
| 831 | while (len > 0) { |
| 832 | block_len = min(len, cntlr.databytes); |
| 833 | if (block_len > (~addr & 0xff)) |
| 834 | block_len = (~addr & 0xff) + 1; |
| 835 | ich_hwseq_set_addr(addr); |
| 836 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 837 | hsfc &= ~HSFC_FCYCLE; /* set read operation */ |
| 838 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 839 | /* set byte count */ |
| 840 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 841 | hsfc |= HSFC_FGO; /* start */ |
| 842 | writew_(hsfc, &cntlr.ich9_spi->hsfc); |
| 843 | |
| 844 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) |
| 845 | return 1; |
| 846 | ich_read_data(buf, block_len); |
| 847 | addr += block_len; |
| 848 | buf += block_len; |
| 849 | len -= block_len; |
| 850 | } |
| 851 | return 0; |
| 852 | } |
| 853 | |
| 854 | /* Fill len bytes from the data array into the fdata/spid registers. |
| 855 | * |
| 856 | * Note that using len > flash->pgm->spi.max_data_write will trash the registers |
| 857 | * following the data registers. |
| 858 | */ |
| 859 | static void ich_fill_data(const uint8_t *data, int len) |
| 860 | { |
| 861 | uint32_t temp32 = 0; |
| 862 | int i; |
| 863 | |
| 864 | if (len <= 0) |
| 865 | return; |
| 866 | |
| 867 | for (i = 0; i < len; i++) { |
| 868 | if ((i % 4) == 0) |
| 869 | temp32 = 0; |
| 870 | |
| 871 | temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); |
| 872 | |
| 873 | if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ |
| 874 | writel_(temp32, cntlr.data + (i - (i % 4))); |
| 875 | } |
| 876 | i--; |
| 877 | if ((i % 4) != 3) /* Write remaining data to regs. */ |
| 878 | writel_(temp32, cntlr.data + (i - (i % 4))); |
| 879 | } |
| 880 | |
| 881 | static int ich_hwseq_write(struct spi_flash *flash, |
| 882 | u32 addr, size_t len, const void *buf) |
| 883 | { |
| 884 | uint16_t hsfc; |
| 885 | uint16_t timeout = 100 * 60; |
| 886 | uint8_t block_len; |
| 887 | uint32_t start = addr; |
| 888 | |
| 889 | if (addr + len > flash->size) { |
| 890 | printk (BIOS_ERR, |
| 891 | "Attempt to write 0x%x-0x%x which is out of chip\n", |
| 892 | (unsigned)addr, (unsigned) (addr+len)); |
| 893 | return -1; |
| 894 | } |
| 895 | |
| 896 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
| 897 | writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); |
| 898 | |
| 899 | while (len > 0) { |
| 900 | block_len = min(len, cntlr.databytes); |
| 901 | if (block_len > (~addr & 0xff)) |
| 902 | block_len = (~addr & 0xff) + 1; |
| 903 | |
| 904 | ich_hwseq_set_addr(addr); |
| 905 | |
| 906 | ich_fill_data(buf, block_len); |
| 907 | hsfc = readw_(&cntlr.ich9_spi->hsfc); |
| 908 | hsfc &= ~HSFC_FCYCLE; /* clear operation */ |
| 909 | hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ |
| 910 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 911 | /* set byte count */ |
| 912 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 913 | hsfc |= HSFC_FGO; /* start */ |
| 914 | writew_(hsfc, &cntlr.ich9_spi->hsfc); |
| 915 | |
| 916 | if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) |
| 917 | { |
| 918 | printk (BIOS_ERR, "SF: write failure at %x\n", |
| 919 | addr); |
| 920 | return -1; |
| 921 | } |
| 922 | addr += block_len; |
| 923 | buf += block_len; |
| 924 | len -= block_len; |
| 925 | } |
| 926 | printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", |
| 927 | (unsigned) (addr - start), start); |
| 928 | return 0; |
| 929 | } |
| 930 | |
| 931 | |
| 932 | static struct spi_flash *spi_flash_hwseq(struct spi_slave *spi) |
| 933 | { |
| 934 | struct spi_flash *flash = NULL; |
| 935 | uint32_t flcomp; |
| 936 | |
| 937 | flash = malloc(sizeof(*flash)); |
| 938 | if (!flash) { |
| 939 | printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); |
| 940 | return NULL; |
| 941 | } |
| 942 | |
| 943 | flash->spi = spi; |
| 944 | flash->name = "Opaque HW-sequencing"; |
| 945 | |
| 946 | flash->write = ich_hwseq_write; |
| 947 | flash->erase = ich_hwseq_erase; |
| 948 | flash->read = ich_hwseq_read; |
| 949 | ich_hwseq_set_addr (0); |
| 950 | switch ((cntlr.hsfs >> 3) & 3) |
| 951 | { |
| 952 | case 0: |
| 953 | flash->sector_size = 256; |
| 954 | break; |
| 955 | case 1: |
| 956 | flash->sector_size = 4096; |
| 957 | break; |
| 958 | case 2: |
| 959 | flash->sector_size = 8192; |
| 960 | break; |
| 961 | case 3: |
| 962 | flash->sector_size = 65536; |
| 963 | break; |
| 964 | } |
| 965 | |
| 966 | writel_ (0x1000, &cntlr.ich9_spi->fdoc); |
| 967 | flcomp = readl_(&cntlr.ich9_spi->fdod); |
| 968 | |
| 969 | flash->size = 1 << (19 + (flcomp & 7)); |
| 970 | |
| 971 | if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) |
| 972 | flash->size += 1 << (19 + ((flcomp >> 3) & 7)); |
| 973 | printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); |
| 974 | |
| 975 | return flash; |
| 976 | } |