Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 2 | |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 3 | #include <assert.h> |
Felix Held | 915c387 | 2023-04-11 21:21:35 +0200 | [diff] [blame] | 4 | #include <amdblocks/acpi.h> |
Michał Żygowski | f65c1e4 | 2019-12-01 18:14:39 +0100 | [diff] [blame] | 5 | #include <amdblocks/biosram.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Felix Held | 4b2464f | 2022-02-23 17:54:20 +0100 | [diff] [blame] | 7 | #include <arch/hpet.h> |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Felix Held | a8da070 | 2023-06-05 21:19:27 +0200 | [diff] [blame] | 9 | #include <arch/vga.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 10 | #include <acpi/acpi.h> |
| 11 | #include <acpi/acpigen.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 12 | #include <cbmem.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 13 | #include <console/console.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 14 | #include <cpu/amd/mtrr.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 15 | #include <cpu/x86/lapic_def.h> |
Marshall Dawson | f82aa10 | 2017-09-20 18:01:41 -0600 | [diff] [blame] | 16 | #include <cpu/x86/msr.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 20 | #include <amdblocks/agesawrapper.h> |
| 21 | #include <amdblocks/agesawrapper_call.h> |
Felix Held | 604ffa6 | 2021-02-12 00:43:20 +0100 | [diff] [blame] | 22 | #include <amdblocks/ioapic.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 23 | #include <agesa_headers.h> |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 24 | #include <soc/cpu.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 25 | #include <soc/northbridge.h> |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 27 | #include <soc/iomap.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 28 | #include <stdint.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 29 | #include <string.h> |
| 30 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 31 | #include "chip.h" |
| 32 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 33 | static void read_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 34 | { |
Felix Held | 56b037b | 2022-03-02 22:57:01 +0100 | [diff] [blame] | 35 | unsigned int idx = 0; |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 36 | |
Felix Held | af17f0b | 2022-03-02 23:36:55 +0100 | [diff] [blame] | 37 | /* The northbridge has no PCI BARs implemented, so there's no need to call |
| 38 | pci_dev_read_resources for it */ |
| 39 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 40 | /* |
| 41 | * This MMCONF resource must be reserved in the PCI domain. |
| 42 | * It is not honored by the coreboot resource allocator if it is in |
| 43 | * the CPU_CLUSTER. |
| 44 | */ |
Felix Held | 56b037b | 2022-03-02 22:57:01 +0100 | [diff] [blame] | 45 | mmconf_resource(dev, idx++); |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 46 | |
| 47 | /* NB IOAPIC2 resource */ |
Felix Held | 8f0075c | 2023-08-09 19:28:39 +0200 | [diff] [blame] | 48 | mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 49 | } |
| 50 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 51 | /** |
| 52 | * I tried to reuse the resource allocation code in set_resource() |
| 53 | * but it is too difficult to deal with the resource allocation magic. |
| 54 | */ |
| 55 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 56 | static void create_vga_resource(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 57 | { |
| 58 | struct bus *link; |
| 59 | |
| 60 | /* find out which link the VGA card is connected, |
| 61 | * we only deal with the 'first' vga card */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 62 | for (link = dev->link_list ; link ; link = link->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 63 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
| 64 | break; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 65 | |
| 66 | /* no VGA card installed */ |
| 67 | if (link == NULL) |
| 68 | return; |
| 69 | |
Marshall Dawson | e2697de | 2017-09-06 10:46:36 -0600 | [diff] [blame] | 70 | printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 71 | /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 72 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 73 | } |
| 74 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 75 | static void set_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 76 | { |
| 77 | struct bus *bus; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 78 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 79 | /* do we need this? */ |
| 80 | create_vga_resource(dev); |
| 81 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 82 | for (bus = dev->link_list ; bus ; bus = bus->next) |
| 83 | if (bus->children) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 84 | assign_resources(bus); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | static void northbridge_init(struct device *dev) |
| 88 | { |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame] | 89 | register_new_ioapic((u8 *)IO_APIC2_ADDR); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 90 | } |
| 91 | |
Felix Held | 8cab80c | 2023-05-05 15:20:15 +0200 | [diff] [blame] | 92 | /* Used by \_SB.PCI0._CRS */ |
| 93 | static void acpi_fill_root_complex_tom(const struct device *device) |
| 94 | { |
| 95 | const char *scope; |
| 96 | |
| 97 | assert(device); |
| 98 | |
| 99 | scope = acpi_device_scope(device); |
| 100 | assert(scope); |
| 101 | acpigen_write_scope(scope); |
| 102 | |
| 103 | acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); |
| 104 | |
| 105 | /* |
| 106 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 107 | * here. |
| 108 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 109 | * slide 22ff. |
| 110 | * Shift value right by 20 bit to make it fit into 32bit, |
| 111 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 112 | */ |
| 113 | acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); |
| 114 | acpigen_pop_len(); |
| 115 | } |
| 116 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 117 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
| 118 | { |
| 119 | void *addr, *current; |
| 120 | |
| 121 | /* Skip the HEST header. */ |
| 122 | current = (void *)(hest + 1); |
| 123 | |
| 124 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 125 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 126 | current += acpi_create_hest_error_source(hest, current, 0, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 127 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 128 | |
| 129 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 130 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 131 | current += acpi_create_hest_error_source(hest, current, 1, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 132 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 133 | |
| 134 | return (unsigned long)current; |
| 135 | } |
| 136 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 137 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 138 | unsigned long current, |
| 139 | acpi_rsdp_t *rsdp) |
| 140 | { |
| 141 | acpi_srat_t *srat; |
| 142 | acpi_slit_t *slit; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 143 | acpi_header_t *alib; |
| 144 | acpi_header_t *ivrs; |
| 145 | acpi_hest_t *hest; |
| 146 | |
| 147 | /* HEST */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 148 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 149 | hest = (acpi_hest_t *)current; |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 150 | acpi_write_hest(hest, acpi_fill_hest); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 151 | acpi_add_table(rsdp, (void *)current); |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 152 | current += hest->header.length; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 153 | |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 154 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 155 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 156 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 157 | if (ivrs != NULL) { |
| 158 | memcpy((void *)current, ivrs, ivrs->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 159 | ivrs = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 160 | current += ivrs->length; |
| 161 | acpi_add_table(rsdp, ivrs); |
| 162 | } else { |
| 163 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 164 | } |
| 165 | |
| 166 | /* SRAT */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 167 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 168 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 169 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 170 | if (srat != NULL) { |
| 171 | memcpy((void *)current, srat, srat->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 172 | srat = (acpi_srat_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 173 | current += srat->header.length; |
| 174 | acpi_add_table(rsdp, srat); |
| 175 | } else { |
| 176 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 177 | } |
| 178 | |
| 179 | /* SLIT */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 180 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 181 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 182 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 183 | if (slit != NULL) { |
| 184 | memcpy((void *)current, slit, slit->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 185 | slit = (acpi_slit_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 186 | current += slit->header.length; |
| 187 | acpi_add_table(rsdp, slit); |
| 188 | } else { |
| 189 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 190 | } |
| 191 | |
| 192 | /* ALIB */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 193 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 194 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 195 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 196 | if (alib != NULL) { |
| 197 | memcpy((void *)current, alib, alib->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 198 | alib = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 199 | current += alib->length; |
| 200 | acpi_add_table(rsdp, (void *)alib); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 201 | } else { |
| 202 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." |
| 203 | " Skipping.\n"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 204 | } |
| 205 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 206 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 207 | return current; |
| 208 | } |
| 209 | |
Felix Held | 26651c8 | 2022-10-13 16:12:40 +0200 | [diff] [blame] | 210 | struct device_operations stoneyridge_northbridge_operations = { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 211 | .read_resources = read_resources, |
| 212 | .set_resources = set_resources, |
| 213 | .enable_resources = pci_dev_enable_resources, |
| 214 | .init = northbridge_init, |
Felix Held | 915c387 | 2023-04-11 21:21:35 +0200 | [diff] [blame] | 215 | .acpi_fill_ssdt = acpi_fill_root_complex_tom, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 216 | .write_acpi_tables = agesa_write_acpi_tables, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 217 | }; |
| 218 | |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 219 | /* |
| 220 | * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET, |
| 221 | * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining |
| 222 | * MMIO to posted. Route all I/O to the southbridge. |
| 223 | */ |
| 224 | void amd_initcpuio(void) |
| 225 | { |
Felix Held | 5e9afe7 | 2023-04-20 12:55:55 +0200 | [diff] [blame] | 226 | uintptr_t topmem = get_top_of_mem_below_4gb(); |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 227 | uintptr_t base, limit; |
| 228 | |
| 229 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
| 230 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
| 231 | |
| 232 | /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ |
| 233 | base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; |
Kyösti Mälkki | dea42e0 | 2021-05-31 20:26:16 +0300 | [diff] [blame] | 234 | limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP; |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 235 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); |
| 236 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); |
| 237 | |
| 238 | /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */ |
| 239 | base = (topmem >> 8) | MMIO_WE | MMIO_RE; |
| 240 | limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8; |
| 241 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit); |
| 242 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base); |
| 243 | |
| 244 | /* Route all I/O downstream */ |
| 245 | base = 0 | IO_WE | IO_RE; |
| 246 | limit = ALIGN_DOWN(0xffff, 4 * KiB); |
| 247 | pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit); |
| 248 | pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base); |
| 249 | } |
| 250 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 251 | void fam15_finalize(void *chip_info) |
| 252 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 253 | u32 value; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 254 | |
| 255 | /* TODO: move IOAPIC code to dsdt.asl */ |
| 256 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0); |
| 257 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 258 | |
| 259 | /* disable No Snoop */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 260 | value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); |
Richard Spiegel | 3d34ae3 | 2018-04-13 13:20:08 -0700 | [diff] [blame] | 261 | value &= ~HDA_NO_SNOOP_EN; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 262 | pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 263 | } |
| 264 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 265 | void domain_enable_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 266 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 267 | /* Must be called after PCI enumeration and resource allocation */ |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 268 | if (!acpi_is_wakeup_s3()) |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 269 | do_agesawrapper(AMD_INIT_MID, "amdinitmid"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 270 | } |
| 271 | |
Furquan Shaikh | fc752b6 | 2020-05-13 12:14:11 -0700 | [diff] [blame] | 272 | void domain_read_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 273 | { |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 274 | uint64_t uma_base = get_uma_base(); |
| 275 | uint32_t uma_size = get_uma_size(); |
| 276 | uint32_t mem_useable = (uintptr_t)cbmem_top(); |
Felix Held | 392cf2f | 2023-04-20 13:23:23 +0200 | [diff] [blame] | 277 | uint32_t tom = get_top_of_mem_below_4gb(); |
Felix Held | 27af3e6 | 2023-04-22 05:59:52 +0200 | [diff] [blame] | 278 | uint64_t high_tom = get_top_of_mem_above_4gb(); |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 279 | uint64_t high_mem_useable; |
| 280 | int idx = 0x10; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 281 | |
Furquan Shaikh | fc752b6 | 2020-05-13 12:14:11 -0700 | [diff] [blame] | 282 | pci_domain_read_resources(dev); |
| 283 | |
Felix Held | d7ad140 | 2023-06-05 15:30:10 +0200 | [diff] [blame] | 284 | fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); |
| 285 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 286 | /* 0x0 -> 0x9ffff */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 287 | ram_range(dev, idx++, 0, 0xa0000); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 288 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 289 | /* 0xa0000 -> 0xbffff: legacy VGA */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 290 | mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 291 | |
| 292 | /* 0xc0000 -> 0xfffff: Option ROM */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 293 | reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 294 | |
Marshall Dawson | 29f1b74 | 2017-09-06 14:59:45 -0600 | [diff] [blame] | 295 | /* |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 296 | * 0x100000 (1MiB) -> low top usable RAM |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 297 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 298 | */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 299 | ram_from_to(dev, idx++, 1 * MiB, mem_useable); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 300 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 301 | /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 302 | reserved_ram_from_to(dev, idx++, mem_useable, tom); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 303 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 304 | /* If there is memory above 4GiB */ |
Felix Held | 392cf2f | 2023-04-20 13:23:23 +0200 | [diff] [blame] | 305 | if (high_tom >> 32) { |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 306 | /* 4GiB -> high top usable */ |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 307 | if (uma_base >= (4ull * GiB)) |
| 308 | high_mem_useable = uma_base; |
| 309 | else |
Felix Held | 392cf2f | 2023-04-20 13:23:23 +0200 | [diff] [blame] | 310 | high_mem_useable = high_tom; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 311 | |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 312 | ram_from_to(dev, idx++, 4ull * GiB, high_mem_useable); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 313 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 314 | /* High top usable RAM -> high top RAM */ |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 315 | if (uma_base >= (4ull * GiB)) { |
Arthur Heymans | 885efa1 | 2023-07-05 12:11:12 +0200 | [diff] [blame] | 316 | reserved_ram_range(dev, idx++, uma_base, uma_size); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 317 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 318 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 319 | } |
| 320 | |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 321 | __weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } |
| 322 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 323 | void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) |
| 324 | { |
Felix Held | 727ee667 | 2023-12-20 22:47:03 +0100 | [diff] [blame] | 325 | params->IommuSupport = is_dev_enabled(DEV_PTR(iommu)); |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 326 | set_board_env_params(params); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | void SetNbMidParams(GNB_MID_CONFIGURATION *params) |
| 330 | { |
| 331 | /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ |
| 332 | params->iGpuVgaMode = 0; |
| 333 | params->GnbIoapicAddress = IO_APIC2_ADDR; |
| 334 | } |