Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Elyes HAOUAS | 9cbf26d | 2021-01-31 08:31:20 +0100 | [diff] [blame] | 4 | #include <arch/pci_io_cfg.h> |
Angel Pons | 10f9b83 | 2021-01-20 14:58:32 +0100 | [diff] [blame] | 5 | #include <assert.h> |
Angel Pons | 10f9b83 | 2021-01-20 14:58:32 +0100 | [diff] [blame] | 6 | #include <types.h> |
Elyes HAOUAS | 9cbf26d | 2021-01-31 08:31:20 +0100 | [diff] [blame] | 7 | |
Arthur Heymans | 360d947 | 2019-11-12 18:11:03 +0100 | [diff] [blame] | 8 | #include "sandybridge.h" |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 9 | |
Angel Pons | 10f9b83 | 2021-01-20 14:58:32 +0100 | [diff] [blame] | 10 | static uint32_t encode_pciexbar_length(void) |
| 11 | { |
| 12 | switch (CONFIG_MMCONF_BUS_NUMBER) { |
| 13 | case 256: return 0 << 1; |
| 14 | case 128: return 1 << 1; |
| 15 | case 64: return 2 << 1; |
| 16 | default: return dead_code_t(uint32_t); |
| 17 | } |
| 18 | } |
| 19 | |
Arthur Heymans | 360d947 | 2019-11-12 18:11:03 +0100 | [diff] [blame] | 20 | void bootblock_early_northbridge_init(void) |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 21 | { |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 22 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 23 | * The "io" variant of the config access is explicitly used to setup the |
Elyes HAOUAS | 98d6f33 | 2021-01-16 14:59:42 +0100 | [diff] [blame] | 24 | * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 25 | * subsequent non-explicit config accesses use MCFG. This code also assumes |
| 26 | * that bootblock_northbridge_init() is the first thing called in the non-asm |
| 27 | * boot block code. The final assumption is that no assembly code is using the |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 28 | * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 29 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 30 | * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 31 | */ |
Elyes HAOUAS | 9cbf26d | 2021-01-31 08:31:20 +0100 | [diff] [blame] | 32 | const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; |
Angel Pons | 10f9b83 | 2021-01-20 14:58:32 +0100 | [diff] [blame] | 33 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); |
Elyes HAOUAS | 9cbf26d | 2021-01-31 08:31:20 +0100 | [diff] [blame] | 34 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 35 | } |