Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 3 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 4 | #include <arch/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Arthur Heymans | 360d947 | 2019-11-12 18:11:03 +0100 | [diff] [blame] | 6 | #include "sandybridge.h" |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 7 | |
Arthur Heymans | 360d947 | 2019-11-12 18:11:03 +0100 | [diff] [blame] | 8 | void bootblock_early_northbridge_init(void) |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 9 | { |
| 10 | uint32_t reg; |
| 11 | |
| 12 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 13 | * The "io" variant of the config access is explicitly used to setup the |
| 14 | * PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to to true. That way, all |
| 15 | * subsequent non-explicit config accesses use MCFG. This code also assumes |
| 16 | * that bootblock_northbridge_init() is the first thing called in the non-asm |
| 17 | * boot block code. The final assumption is that no assembly code is using the |
Elyes HAOUAS | 0c9630e | 2020-01-07 20:06:08 +0100 | [diff] [blame] | 18 | * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 19 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 20 | * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 21 | */ |
| 22 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 23 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 24 | reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 25 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 26 | } |