nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h>
Also rename 'reg' to 'reg32'.
Change-Id: I3aca03dfe20dd0a61cba3ba55146f76e412a2c5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 529f4f8..92f9aee 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
+#include <arch/pci_io_cfg.h>
#include <assert.h>
-#include <device/pci_ops.h>
#include <types.h>
+
#include "sandybridge.h"
static uint32_t encode_pciexbar_length(void)
@@ -28,7 +29,7 @@
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
- const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
- pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
+ pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}