nb/intel/sandybridge: Tidy up code and comments
- Reformat some lines of code
- Move MCHBAR registers and documentation into a separate file
- Add a few missing macros
- Rename some registers
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
With BUILD_TIMELESS=1, this commit does not change the result of:
- Asus P8Z77-V LX2 with native raminit.
- Asus P8Z77-M PRO with MRC raminit.
Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index b6ba395..9dfeed6 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -20,19 +20,17 @@
uint32_t reg;
/*
- * The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
- * to true. That way all subsequent non-explicit config accesses use
- * MCFG. This code also assumes that bootblock_northbridge_init() is
- * the first thing called in the non-asm boot block code. The final
- * assumption is that no assembly code is using the
+ * The "io" variant of the config access is explicitly used to setup the
+ * PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to to true. That way, all
+ * subsequent non-explicit config accesses use MCFG. This code also assumes
+ * that bootblock_northbridge_init() is the first thing called in the non-asm
+ * boot block code. The final assumption is that no assembly code is using the
* CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
*
- * The PCIEXBAR is assumed to live in the memory mapped IO space under
- * 4GiB.
+ * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
reg = 0;
- pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg);
+ pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
- pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
+ pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
}