Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 2 | |
Furquan Shaikh | 583ba8b | 2020-06-30 23:51:24 -0700 | [diff] [blame] | 3 | #include <acpi/acpi_device.h> |
| 4 | #include <acpi/acpigen.h> |
Karthikeyan Ramasubramanian | 4520aa2 | 2021-04-23 11:42:19 -0600 | [diff] [blame] | 5 | #include <amdblocks/acp.h> |
| 6 | #include <amdblocks/acpimmio.h> |
| 7 | #include <amdblocks/chip.h> |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 8 | #include <console/console.h> |
| 9 | #include <device/device.h> |
Felix Held | e5d3b4e | 2021-04-20 00:39:55 +0200 | [diff] [blame] | 10 | #include <device/mmio.h> |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
| 13 | #include <device/pci_ops.h> |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 14 | #include <commonlib/helpers.h> |
| 15 | |
Karthikeyan Ramasubramanian | 4520aa2 | 2021-04-23 11:42:19 -0600 | [diff] [blame] | 16 | /* ACP registers and associated fields */ |
| 17 | #define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ |
| 18 | #define PIN_CONFIG_MASK (7 << 0) |
| 19 | #define ACP_I2S_WAKE_EN 0x1414 |
| 20 | #define WAKE_EN_MASK (1 << 0) |
| 21 | #define ACP_PME_EN 0x1418 |
| 22 | #define PME_EN_MASK (1 << 0) |
| 23 | |
Felix Held | 349a145 | 2021-04-20 00:38:32 +0200 | [diff] [blame] | 24 | static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set) |
Akshu Agrawal | 42d4a57 | 2019-12-16 15:13:17 +0530 | [diff] [blame] | 25 | { |
Felix Held | e5d3b4e | 2021-04-20 00:39:55 +0200 | [diff] [blame] | 26 | clrsetbits32((void *)(bar + reg), clear, set); |
Akshu Agrawal | 42d4a57 | 2019-12-16 15:13:17 +0530 | [diff] [blame] | 27 | } |
| 28 | |
Aaron Durbin | a6e3b5a | 2020-06-09 07:56:43 -0600 | [diff] [blame] | 29 | static void init(struct device *dev) |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 30 | { |
Karthikeyan Ramasubramanian | 4520aa2 | 2021-04-23 11:42:19 -0600 | [diff] [blame] | 31 | const struct soc_amd_common_config *cfg = soc_get_common_config(); |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 32 | struct resource *res; |
| 33 | uintptr_t bar; |
| 34 | |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 35 | res = dev->resource_list; |
| 36 | if (!res || !res->base) { |
| 37 | printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); |
| 38 | return; |
| 39 | } |
| 40 | |
Karthikeyan Ramasubramanian | 4520aa2 | 2021-04-23 11:42:19 -0600 | [diff] [blame] | 41 | /* Set the proper I2S_PIN_CONFIG state */ |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 42 | bar = (uintptr_t)res->base; |
Karthikeyan Ramasubramanian | 4520aa2 | 2021-04-23 11:42:19 -0600 | [diff] [blame] | 43 | acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg); |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 44 | |
Akshu Agrawal | 42d4a57 | 2019-12-16 15:13:17 +0530 | [diff] [blame] | 45 | /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ |
Karthikeyan Ramasubramanian | 4520aa2 | 2021-04-23 11:42:19 -0600 | [diff] [blame] | 46 | acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable); |
| 47 | acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable); |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 48 | } |
| 49 | |
Furquan Shaikh | 0d787a1 | 2020-06-18 22:20:52 -0700 | [diff] [blame] | 50 | static const char *acp_acpi_name(const struct device *dev) |
| 51 | { |
| 52 | return "ACPD"; |
| 53 | } |
| 54 | |
Karthikeyan Ramasubramanian | 4ce48b3 | 2021-05-27 16:25:28 -0600 | [diff] [blame^] | 55 | static void acp_fill_wov_method(const struct device *dev) |
| 56 | { |
| 57 | const struct soc_amd_common_config *cfg = soc_get_common_config(); |
| 58 | const char *scope = acpi_device_path(dev); |
| 59 | |
| 60 | if (!cfg->acp_config.dmic_present || !scope) |
| 61 | return; |
| 62 | |
| 63 | /* For ACP DMIC hardware runtime detection on the platform, _WOV method is populated. */ |
| 64 | acpigen_write_scope(scope); /* Scope */ |
| 65 | acpigen_write_method("_WOV", 0); |
| 66 | acpigen_write_return_integer(1); |
| 67 | acpigen_write_method_end(); |
| 68 | acpigen_write_scope_end(); |
| 69 | } |
| 70 | |
| 71 | static void acp_fill_ssdt(const struct device *dev) |
| 72 | { |
| 73 | acpi_device_write_pci_dev(dev); |
| 74 | acp_fill_wov_method(dev); |
| 75 | } |
| 76 | |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 77 | static struct device_operations acp_ops = { |
| 78 | .read_resources = pci_dev_read_resources, |
| 79 | .set_resources = pci_dev_set_resources, |
Aaron Durbin | a6e3b5a | 2020-06-09 07:56:43 -0600 | [diff] [blame] | 80 | .enable_resources = pci_dev_enable_resources, |
| 81 | .init = init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 82 | .ops_pci = &pci_dev_ops_pci, |
Furquan Shaikh | de4baff | 2020-07-16 13:26:44 -0700 | [diff] [blame] | 83 | .scan_bus = scan_static_bus, |
Furquan Shaikh | 0d787a1 | 2020-06-18 22:20:52 -0700 | [diff] [blame] | 84 | .acpi_name = acp_acpi_name, |
Karthikeyan Ramasubramanian | 4ce48b3 | 2021-05-27 16:25:28 -0600 | [diff] [blame^] | 85 | .acpi_fill_ssdt = acp_fill_ssdt, |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | static const struct pci_driver acp_driver __pci_driver = { |
| 89 | .ops = &acp_ops, |
| 90 | .vendor = PCI_VENDOR_ID_AMD, |
Furquan Shaikh | a1cd7eb | 2020-04-15 23:58:22 -0700 | [diff] [blame] | 91 | .device = PCI_DEVICE_ID_AMD_FAM17H_ACP, |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 92 | }; |