Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 2 | |
Furquan Shaikh | 583ba8b | 2020-06-30 23:51:24 -0700 | [diff] [blame^] | 3 | #include <acpi/acpi_device.h> |
| 4 | #include <acpi/acpigen.h> |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
| 9 | #include <device/pci_ops.h> |
| 10 | #include "chip.h" |
Raul E Rangel | 4c7e0d7 | 2020-05-07 15:14:09 -0600 | [diff] [blame] | 11 | #include <soc/acp.h> |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 12 | #include <soc/acpi.h> |
| 13 | #include <soc/pci_devs.h> |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 14 | #include <soc/southbridge.h> |
| 15 | #include <amdblocks/acpimmio.h> |
| 16 | #include <commonlib/helpers.h> |
| 17 | |
Aaron Durbin | a6e3b5a | 2020-06-09 07:56:43 -0600 | [diff] [blame] | 18 | static void init(struct device *dev) |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 19 | { |
| 20 | const struct soc_amd_picasso_config *cfg; |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 21 | struct resource *res; |
| 22 | uintptr_t bar; |
| 23 | |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 24 | /* Set the proper I2S_PIN_CONFIG state */ |
Felix Held | 7180090 | 2020-06-17 19:59:53 +0200 | [diff] [blame] | 25 | cfg = config_of_soc(); |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 26 | |
| 27 | res = dev->resource_list; |
| 28 | if (!res || !res->base) { |
| 29 | printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); |
| 30 | return; |
| 31 | } |
| 32 | |
| 33 | bar = (uintptr_t)res->base; |
| 34 | write32((void *)(bar + ACP_I2S_PIN_CONFIG), cfg->acp_pin_cfg); |
| 35 | |
| 36 | if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) |
| 37 | sb_clk_output_48Mhz(); /* Internal connection to I2S */ |
| 38 | } |
| 39 | |
Furquan Shaikh | 0d787a1 | 2020-06-18 22:20:52 -0700 | [diff] [blame] | 40 | static const char *acp_acpi_name(const struct device *dev) |
| 41 | { |
| 42 | return "ACPD"; |
| 43 | } |
| 44 | |
Furquan Shaikh | 583ba8b | 2020-06-30 23:51:24 -0700 | [diff] [blame^] | 45 | #define AMD_I2S_ACPI_NAME "I2SM" |
| 46 | #define AMD_I2S_ACPI_HID "AMDI5682" |
| 47 | #define AMD_I2S_ACPI_DESC "I2S machine driver" |
| 48 | |
| 49 | static void acp_fill_i2s_machine_dev(const struct device *dev) |
| 50 | { |
| 51 | const char *scope = acpi_device_path(dev); |
| 52 | const struct soc_amd_picasso_config *cfg = config_of_soc(); |
| 53 | const struct acpi_gpio *dmic_select_gpio = &cfg->dmic_select_gpio; |
| 54 | struct acpi_dp *dsd; |
| 55 | |
| 56 | if (dmic_select_gpio->pin_count == 0) |
| 57 | return; |
| 58 | |
| 59 | acpigen_write_scope(scope); /* Scope */ |
| 60 | acpigen_write_device(AMD_I2S_ACPI_NAME); /* Device */ |
| 61 | acpigen_write_name_string("_HID", AMD_I2S_ACPI_HID); |
| 62 | acpigen_write_name_integer("_UID", 1); |
| 63 | acpigen_write_name_string("_DDN", AMD_I2S_ACPI_DESC); |
| 64 | |
| 65 | acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); |
| 66 | |
| 67 | /* Resources */ |
| 68 | acpigen_write_name("_CRS"); |
| 69 | acpigen_write_resourcetemplate_header(); |
| 70 | acpi_device_write_gpio(dmic_select_gpio); |
| 71 | acpigen_write_resourcetemplate_footer(); |
| 72 | |
| 73 | dsd = acpi_dp_new_table("_DSD"); |
| 74 | /* |
| 75 | * This GPIO is used to select DMIC0 or DMIC1 by the kernel driver. It does not |
| 76 | * really have a polarity since low and high control the selection of DMIC and |
| 77 | * hence does not have an active polarity. |
| 78 | * Kernel driver does not use the polarity field and instead treats the GPIO |
| 79 | * selection as follows: |
| 80 | * Set low (0) = Select DMIC0 |
| 81 | * Set high (1) = Select DMIC1 |
| 82 | */ |
| 83 | acpi_dp_add_gpio(dsd, "dmic-gpios", acpi_device_path_join(dev, AMD_I2S_ACPI_NAME), |
| 84 | 0, /* Index = 0 (There is a single GPIO entry in _CRS). */ |
| 85 | 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ |
| 86 | 0); /* Active low = 0 (Kernel driver does not use active polarity). */ |
| 87 | acpi_dp_write(dsd); |
| 88 | |
| 89 | acpigen_pop_len(); /* Device */ |
| 90 | acpigen_pop_len(); /* Scope */ |
| 91 | } |
| 92 | |
| 93 | static void acp_fill_ssdt(const struct device *dev) |
| 94 | { |
| 95 | acpi_device_write_pci_dev(dev); |
| 96 | acp_fill_i2s_machine_dev(dev); |
| 97 | } |
| 98 | |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 99 | static struct device_operations acp_ops = { |
| 100 | .read_resources = pci_dev_read_resources, |
| 101 | .set_resources = pci_dev_set_resources, |
Aaron Durbin | a6e3b5a | 2020-06-09 07:56:43 -0600 | [diff] [blame] | 102 | .enable_resources = pci_dev_enable_resources, |
| 103 | .init = init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 104 | .ops_pci = &pci_dev_ops_pci, |
Furquan Shaikh | 0d787a1 | 2020-06-18 22:20:52 -0700 | [diff] [blame] | 105 | .acpi_name = acp_acpi_name, |
Furquan Shaikh | 583ba8b | 2020-06-30 23:51:24 -0700 | [diff] [blame^] | 106 | .acpi_fill_ssdt = acp_fill_ssdt, |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 107 | }; |
| 108 | |
| 109 | static const struct pci_driver acp_driver __pci_driver = { |
| 110 | .ops = &acp_ops, |
| 111 | .vendor = PCI_VENDOR_ID_AMD, |
Furquan Shaikh | a1cd7eb | 2020-04-15 23:58:22 -0700 | [diff] [blame] | 112 | .device = PCI_DEVICE_ID_AMD_FAM17H_ACP, |
Marshall Dawson | 3edc9e2 | 2019-08-16 08:45:20 -0600 | [diff] [blame] | 113 | }; |