soc/amd/picasso: Add audio processor
Add a driver that can properly configure the pads needed to run the
correct audio mode. I2S requires the 48M oscillator enabled
regardless of an external connection.
Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c
new file mode 100644
index 0000000..ad5333a
--- /dev/null
+++ b/src/soc/amd/picasso/acp.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+#include <soc/acpi.h>
+#include <soc/pci_devs.h>
+#include <soc/northbridge.h>
+#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
+#include <commonlib/helpers.h>
+
+static void enable(struct device *dev)
+{
+ const struct soc_amd_picasso_config *cfg;
+ const struct device *nb_dev = pcidev_path_on_root(GNB_DEVFN);
+ struct resource *res;
+ uintptr_t bar;
+
+ pci_dev_enable_resources(dev);
+
+ /* Set the proper I2S_PIN_CONFIG state */
+ if (!nb_dev || !nb_dev->chip_info)
+ return;
+
+ cfg = nb_dev->chip_info;
+
+ res = dev->resource_list;
+ if (!res || !res->base) {
+ printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__);
+ return;
+ }
+
+ bar = (uintptr_t)res->base;
+ write32((void *)(bar + ACP_I2S_PIN_CONFIG), cfg->acp_pin_cfg);
+
+ if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM)
+ sb_clk_output_48Mhz(); /* Internal connection to I2S */
+}
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations acp_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = enable,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver acp_driver __pci_driver = {
+ .ops = &acp_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICD_ID_AMD_PCO_ACP,
+};