Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | ifeq ($(CONFIG_SOC_AMD_GENOA),y) |
| 3 | |
Arthur Heymans | e4eba13 | 2023-07-13 14:02:42 +0200 | [diff] [blame] | 4 | all-y += mmap_boot.c |
Arthur Heymans | b4aaa6f | 2023-07-13 14:11:18 +0200 | [diff] [blame] | 5 | all-y += reset.c |
Arthur Heymans | c5c35ce | 2023-07-13 14:05:08 +0200 | [diff] [blame] | 6 | all-y += config.c |
Varshit Pandya | 95d78d9 | 2023-10-04 19:30:21 +0530 | [diff] [blame] | 7 | all-y += gpio.c |
Varshit Pandya | 970d770 | 2023-10-06 18:14:02 +0530 | [diff] [blame] | 8 | all-y += uart.c |
Arthur Heymans | e4eba13 | 2023-07-13 14:02:42 +0200 | [diff] [blame] | 9 | |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 10 | bootblock-y += early_fch.c |
Arthur Heymans | 4da9d6b4 | 2023-07-13 14:19:09 +0200 | [diff] [blame] | 11 | bootblock-y += aoac.c |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 12 | |
| 13 | romstage-y += romstage.c |
| 14 | |
Arthur Heymans | 4da9d6b4 | 2023-07-13 14:19:09 +0200 | [diff] [blame] | 15 | ramstage-y += aoac.c |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 16 | ramstage-y += chip.c |
Arthur Heymans | 2e2f166 | 2023-07-14 22:58:49 +0200 | [diff] [blame] | 17 | ramstage-y += cpu.c |
Felix Held | 926887c | 2023-10-13 21:19:53 +0200 | [diff] [blame] | 18 | ramstage-y += domain.c |
Felix Held | be9fcf1 | 2023-08-23 22:15:39 +0200 | [diff] [blame] | 19 | ramstage-y += root_complex.c |
Arthur Heymans | 2e2f166 | 2023-07-14 22:58:49 +0200 | [diff] [blame] | 20 | ramstage-y += smihandler.c |
Arthur Heymans | 447e279 | 2023-07-14 23:05:46 +0200 | [diff] [blame^] | 21 | ramstage-y += mca.c |
Arthur Heymans | 2e2f166 | 2023-07-14 22:58:49 +0200 | [diff] [blame] | 22 | |
| 23 | smm-y += smihandler.c |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 24 | |
| 25 | CPPFLAGS_common += -I$(src)/soc/amd/genoa/include |
| 26 | |
Arthur Heymans | 926d55c | 2023-07-13 12:50:45 +0200 | [diff] [blame] | 27 | ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1) |
| 28 | CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000 |
| 29 | endif |
| 30 | |
Arthur Heymans | 8f1c707 | 2023-07-13 12:52:49 +0200 | [diff] [blame] | 31 | # |
| 32 | # PSP Directory Table items |
| 33 | # |
| 34 | # Certain ordering requirements apply, however these are ensured by amdfwtool. |
| 35 | # For more information see "AMD Platform Security Processor BIOS Implementation |
| 36 | # Guide for Server EPYC Processors" #57299 |
| 37 | # |
| 38 | |
| 39 | FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') |
| 40 | |
| 41 | ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) |
| 42 | PSP_SOFTFUSE_BITS += 7 |
| 43 | endif |
| 44 | |
| 45 | ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) |
| 46 | # Enable secure debug unlock |
| 47 | PSP_SOFTFUSE_BITS += 0 |
| 48 | OPT_TOKEN_UNLOCK="--token-unlock" |
| 49 | endif |
| 50 | |
| 51 | # Use additional Soft Fuse bits specified in Kconfig |
| 52 | PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) |
| 53 | |
| 54 | # type = 0x3a |
| 55 | ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) |
| 56 | PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) |
| 57 | endif |
| 58 | |
| 59 | # type = 0x55 |
Arthur Heymans | 8f1c707 | 2023-07-13 12:52:49 +0200 | [diff] [blame] | 60 | SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) |
Arthur Heymans | 8f1c707 | 2023-07-13 12:52:49 +0200 | [diff] [blame] | 61 | |
| 62 | # |
| 63 | # BIOS Directory Table items - proper ordering is managed by amdfwtool |
| 64 | # |
| 65 | |
| 66 | # type = 0x60 |
| 67 | PSP_APCB_FILES=$(APCB_SOURCES) $(APCB1_SOURCES) $(APCB_SOURCES_RECOVERY) $(APCB_SOURCES_RECOVERY1) $(APCB_SOURCES_RECOVERY2) |
| 68 | |
| 69 | # type = 0x61 |
| 70 | PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) |
| 71 | |
| 72 | # type = 0x62 |
| 73 | PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img |
| 74 | PSP_ELF_FILE=$(objcbfs)/bootblock.elf |
| 75 | PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') |
| 76 | PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') |
| 77 | |
| 78 | # Helper function to return a value with given bit set |
| 79 | # Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions. |
| 80 | set-bit=$(call int-shift-left, 1 $(call _toint,$1)) |
| 81 | PSP_SOFTFUSE=$(shell A=$(call int-add, \ |
Matt DeVillier | 0daefa5 | 2023-10-30 20:58:41 -0500 | [diff] [blame] | 82 | $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) |
Arthur Heymans | 8f1c707 | 2023-07-13 12:52:49 +0200 | [diff] [blame] | 83 | |
| 84 | # |
| 85 | # Build the arguments to amdfwtool (order is unimportant). Missing file names |
| 86 | # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. |
| 87 | # |
| 88 | |
| 89 | add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) |
| 90 | |
| 91 | OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ |
| 92 | $(if $(APCB_SOURCES1), --instance 1 --apcb $(APCB_SOURCES1)) \ |
| 93 | $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ |
| 94 | $(if $(APCB_SOURCES_RECOVERY1), --instance 18 --apcb $(APCB_SOURCES_RECOVERY1)) \ |
| 95 | $(if $(APCB_SOURCES_RECOVERY2), --instance 19 --apcb $(APCB_SOURCES_RECOVERY2)) \ |
| 96 | $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) |
| 97 | |
| 98 | OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) |
| 99 | OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) |
| 100 | OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) |
| 101 | OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) |
| 102 | |
| 103 | OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) |
| 104 | OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) |
| 105 | OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) |
| 106 | OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) |
| 107 | |
| 108 | OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) |
| 109 | OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) |
| 110 | |
| 111 | AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ |
| 112 | $(OPT_APOB_ADDR) \ |
| 113 | $(OPT_DEBUG_AMDFWTOOL) \ |
| 114 | $(OPT_PSP_BIOSBIN_FILE) \ |
| 115 | $(OPT_PSP_BIOSBIN_DEST) \ |
| 116 | $(OPT_PSP_BIOSBIN_SIZE) \ |
| 117 | $(OPT_PSP_SOFTFUSE) \ |
| 118 | --use-pspsecureos \ |
| 119 | $(OPT_TOKEN_UNLOCK) \ |
| 120 | $(OPT_WHITELIST_FILE) \ |
| 121 | $(OPT_SPL_TABLE_FILE) \ |
| 122 | $(OPT_EFS_SPI_READ_MODE) \ |
| 123 | $(OPT_EFS_SPI_SPEED) \ |
| 124 | $(OPT_EFS_SPI_MICRON_FLAG) \ |
| 125 | --config $(CONFIG_AMDFW_CONFIG_FILE) \ |
| 126 | --flashsize 0x1000000 |
| 127 | |
| 128 | $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ |
| 129 | $$(PSP_APCB_FILES) \ |
| 130 | $(DEP_FILES) \ |
| 131 | $(AMDFWTOOL) \ |
| 132 | $(obj)/fmap_config.h \ |
| 133 | $(objcbfs)/bootblock.elf # this target also creates the .map file |
| 134 | $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) |
| 135 | rm -f $@ |
| 136 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 137 | $(AMDFWTOOL) \ |
| 138 | $(AMDFW_COMMON_ARGS) \ |
| 139 | --location $(CONFIG_AMD_FWM_POSITION) \ |
| 140 | --multilevel \ |
| 141 | --output $@ |
| 142 | |
| 143 | $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) |
| 144 | rm -f $@ |
| 145 | @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" |
| 146 | $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ |
| 147 | --maxsize $(PSP_BIOSBIN_SIZE) |
| 148 | |
Arthur Heymans | 6d3682e | 2023-07-13 12:34:04 +0200 | [diff] [blame] | 149 | endif |