| commit | 970d7701c77f7d2f3b9691bc2644b2812caa1228 | [log] [tgz] |
|---|---|---|
| author | Varshit Pandya <pandyavarshit@gmail.com> | Fri Oct 06 18:14:02 2023 +0530 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Wed Oct 11 17:49:32 2023 +0000 |
| tree | 290c4325e0e3bd8dedfeb43f3a192b327a778cab | |
| parent | 95d78d9e421e627c5c346b4f1f5600998d71a591 [diff] [blame] |
soc/amd/genoa: Enable uart Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76507 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index a35146c..ef8f349 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc
@@ -5,6 +5,7 @@ all-y += reset.c all-y += config.c all-y += gpio.c +all-y += uart.c bootblock-y += early_fch.c bootblock-y += aoac.c