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Angel Ponsba38f372020-04-05 15:46:45 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Lee Leahy77ff0b12015-05-05 15:07:29 -07002
Lee Leahy32471722015-04-20 15:20:28 -07003#include "chip.h"
Lee Leahy77ff0b12015-05-05 15:07:29 -07004#include <console/console.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -07005#include <device/device.h>
6#include <device/pci.h>
7#include <device/pci_ids.h>
Matt DeVillier132bbe62017-07-01 13:02:47 -05008#include <drivers/intel/gma/opregion.h>
Matt DeVillier8ff2ecd2020-03-29 16:58:48 -05009#include <drivers/intel/gma/i915.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070010#include <reg_script.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070011#include <soc/gfx.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070012#include <soc/pci_devs.h>
13#include <soc/ramstage.h>
14
Lee Leahy77ff0b12015-05-05 15:07:29 -070015static const struct reg_script gpu_pre_vbios_script[] = {
16 /* Make sure GFX is bus master with MMIO access */
Angel Pons89739ba2020-07-25 02:46:39 +020017 REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY),
Lee Leahy77ff0b12015-05-05 15:07:29 -070018 REG_SCRIPT_END
19};
20
21static const struct reg_script gfx_post_vbios_script[] = {
Lee Leahy77ff0b12015-05-05 15:07:29 -070022 /* Set Lock bits */
Angel Ponsaee7ab22020-03-19 00:31:58 +010023 REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK),
Lee Leahy32471722015-04-20 15:20:28 -070024 REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK),
25 REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK),
Lee Leahy77ff0b12015-05-05 15:07:29 -070026 REG_SCRIPT_END
27};
28
Angel Ponsaee7ab22020-03-19 00:31:58 +010029static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)
Lee Leahy77ff0b12015-05-05 15:07:29 -070030{
31 reg_script_run_on_dev(dev, ops);
32}
33
Elyes HAOUASb13fac32018-05-24 22:29:44 +020034static void gfx_pre_vbios_init(struct device *dev)
Lee Leahy77ff0b12015-05-05 15:07:29 -070035{
36 printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
37 gfx_run_script(dev, gpu_pre_vbios_script);
38}
39
Elyes HAOUASb13fac32018-05-24 22:29:44 +020040static void gfx_post_vbios_init(struct device *dev)
Lee Leahy77ff0b12015-05-05 15:07:29 -070041{
42 printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
43 gfx_run_script(dev, gfx_post_vbios_script);
44}
45
Elyes HAOUASb13fac32018-05-24 22:29:44 +020046static void gfx_init(struct device *dev)
Lee Leahy77ff0b12015-05-05 15:07:29 -070047{
Nico Huberf2a0be22020-04-26 17:01:25 +020048 intel_gma_init_igd_opregion();
49
Julius Wernercd49cce2019-03-05 16:53:33 -080050 if (!CONFIG(RUN_FSP_GOP)) {
Matt DeVilliera9492a62018-06-20 00:40:48 -050051 /* Pre VBIOS Init */
52 gfx_pre_vbios_init(dev);
Lee Leahy77ff0b12015-05-05 15:07:29 -070053
Matt DeVilliera9492a62018-06-20 00:40:48 -050054 /* Run VBIOS */
55 pci_dev_init(dev);
Lee Leahy77ff0b12015-05-05 15:07:29 -070056
Matt DeVilliera9492a62018-06-20 00:40:48 -050057 /* Post VBIOS Init */
58 gfx_post_vbios_init(dev);
59 }
Lee Leahy77ff0b12015-05-05 15:07:29 -070060}
61
Furquan Shaikh7536a392020-04-24 21:59:21 -070062static void gma_generate_ssdt(const struct device *dev)
Matt DeVillier8ff2ecd2020-03-29 16:58:48 -050063{
64 const struct soc_intel_braswell_config *chip = dev->chip_info;
65
66 drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
67}
68
Lee Leahy77ff0b12015-05-05 15:07:29 -070069static struct device_operations gfx_device_ops = {
Nico Huber1ef80142015-11-05 23:27:06 +010070 .read_resources = pci_dev_read_resources,
Lee Leahy77ff0b12015-05-05 15:07:29 -070071 .set_resources = pci_dev_set_resources,
72 .enable_resources = pci_dev_enable_resources,
73 .init = gfx_init,
74 .ops_pci = &soc_pci_ops,
Matt DeVillier8ff2ecd2020-03-29 16:58:48 -050075 .acpi_fill_ssdt = gma_generate_ssdt,
Lee Leahy77ff0b12015-05-05 15:07:29 -070076};
77
78static const struct pci_driver gfx_driver __pci_driver = {
79 .ops = &gfx_device_ops,
Felix Singer43b7f412022-03-07 04:34:52 +010080 .vendor = PCI_VID_INTEL,
Lee Leahy77ff0b12015-05-05 15:07:29 -070081 .device = GFX_DEVID,
82};