Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <reg_script.h> |
| 27 | #include <stdlib.h> |
| 28 | |
| 29 | #include <soc/gfx.h> |
| 30 | #include <soc/iosf.h> |
| 31 | #include <soc/pci_devs.h> |
| 32 | #include <soc/ramstage.h> |
| 33 | |
| 34 | #include "chip.h" |
| 35 | |
| 36 | #define GFX_TIMEOUT 100000 /* 100ms */ |
| 37 | |
| 38 | /* |
| 39 | * Lock Power Context Base Register to point to a 24KB block |
| 40 | * of memory in GSM. Power context save data is stored here. |
| 41 | */ |
| 42 | static void gfx_lock_pcbase(device_t dev) |
| 43 | { |
| 44 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 45 | const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, |
| 46 | 288,320,352,384,416,448,480,512 }; |
| 47 | u32 pcsize = 24 << 10; /* 24KB */ |
| 48 | u32 wopcmsz = 0x100000; /* PAVP offset */ |
| 49 | u32 gms, gmsize, pcbase; |
| 50 | |
| 51 | gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK; |
| 52 | gms >>= 3; |
| 53 | if (gms > ARRAY_SIZE(gms_size_map)) |
| 54 | return; |
| 55 | gmsize = gms_size_map[gms]; |
| 56 | |
| 57 | /* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */ |
| 58 | pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000; |
| 59 | pcbase += (gmsize-1) * wopcmsz - pcsize; |
| 60 | pcbase |= 1; /* Lock */ |
| 61 | |
| 62 | write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase); |
| 63 | } |
| 64 | |
| 65 | static const struct reg_script gfx_init_script[] = { |
| 66 | /* Allow-Wake render/media wells */ |
| 67 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1), |
| 68 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT), |
| 69 | /* Render Force-Wake */ |
| 70 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), |
| 71 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, |
| 72 | GFX_TIMEOUT), |
| 73 | /* Media Force-Wake */ |
| 74 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), |
| 75 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, |
| 76 | GFX_TIMEOUT), |
| 77 | /* Workaround - X0:261954/A0:261955 */ |
| 78 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), |
| 79 | |
| 80 | /* |
| 81 | * PowerMeter Weights |
| 82 | */ |
| 83 | |
| 84 | /* SET1 */ |
| 85 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000), |
| 86 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000), |
| 87 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A), |
| 88 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000), |
| 89 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900), |
| 90 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000), |
| 91 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000), |
| 92 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F), |
| 93 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000), |
| 94 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00), |
| 95 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016), |
| 96 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000), |
| 97 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100), |
| 98 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51), |
| 99 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000), |
| 100 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307), |
| 101 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000), |
| 102 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000), |
| 103 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000), |
| 104 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000), |
| 105 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800), |
| 106 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00), |
| 107 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021), |
| 108 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000), |
| 109 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000), |
| 110 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF), |
| 111 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000), |
| 112 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000), |
| 113 | /* SET2 */ |
| 114 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000), |
| 115 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000), |
| 116 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000), |
| 117 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000), |
| 118 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000), |
| 119 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000), |
| 120 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000), |
| 121 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F), |
| 122 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000), |
| 123 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00), |
| 124 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016), |
| 125 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000), |
| 126 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100), |
| 127 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51), |
| 128 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000), |
| 129 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307), |
| 130 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000), |
| 131 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000), |
| 132 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000), |
| 133 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000), |
| 134 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800), |
| 135 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000), |
| 136 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000), |
| 137 | /* SET3 */ |
| 138 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000), |
| 139 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000), |
| 140 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000), |
| 141 | /* Enable PowerMeter Counters */ |
| 142 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058), |
| 143 | |
| 144 | /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ |
| 145 | /* SDP Profile 4 == 0x11940, others 0xcf08 */ |
| 146 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08), |
| 147 | |
| 148 | /* GfxPause */ |
| 149 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388), |
| 150 | |
| 151 | /* Dynamic EU Control Settings */ |
| 152 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004), |
| 153 | |
| 154 | /* Lock ECO Bit Settings */ |
| 155 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000), |
| 156 | |
| 157 | /* DOP Clock Gating */ |
| 158 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001), |
| 159 | |
| 160 | /* MBCunit will send the VCR (Fuse) writes as NP-W */ |
| 161 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000), |
| 162 | |
| 163 | /* |
| 164 | * RC6 Settings |
| 165 | */ |
| 166 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000), |
| 167 | /* RC1e - RC6/6p - RC6pp Wake Rate Limits */ |
| 168 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000), |
| 169 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848), |
| 170 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019), |
| 171 | /* RC Sleep / RCx Thresholds */ |
| 172 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000), |
| 173 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557), |
| 174 | |
| 175 | /* |
| 176 | * Turbo Settings |
| 177 | */ |
| 178 | |
| 179 | /* Render/Video/Blitter Idle Max Count */ |
| 180 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A), |
| 181 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A), |
| 182 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A), |
| 183 | /* RP Down Timeout */ |
| 184 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240), |
| 185 | |
| 186 | /* |
| 187 | * Turbo Control Settings |
| 188 | */ |
| 189 | |
| 190 | /* RP Up/Down Threshold */ |
| 191 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8), |
| 192 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08), |
| 193 | /* RP Up/Down EI */ |
| 194 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0), |
| 195 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730), |
| 196 | |
| 197 | /* RP Idle Hysteresis */ |
| 198 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a), |
| 199 | |
| 200 | /* HW RC6 Control Settings */ |
| 201 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000), |
| 202 | |
| 203 | /* RP Control */ |
| 204 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592), |
| 205 | |
| 206 | /* Enable PM Interrupts */ |
| 207 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000), |
| 208 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), |
| 209 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e), |
| 210 | |
| 211 | /* Aggressive Clock Gating */ |
| 212 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0), |
| 213 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0), |
| 214 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0), |
| 215 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0), |
| 216 | |
| 217 | /* Enable Gfx Turbo. */ |
| 218 | REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG, |
| 219 | ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0), |
| 220 | REG_SCRIPT_END |
| 221 | }; |
| 222 | |
| 223 | static const struct reg_script gpu_pre_vbios_script[] = { |
| 224 | /* Make sure GFX is bus master with MMIO access */ |
| 225 | REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), |
| 226 | /* Display */ |
| 227 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), |
| 228 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, |
| 229 | GFX_TIMEOUT), |
| 230 | /* Tx/Rx Lanes */ |
| 231 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), |
| 232 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, |
| 233 | GFX_TIMEOUT), |
| 234 | /* Common Lane */ |
| 235 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), |
| 236 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, |
| 237 | GFX_TIMEOUT), |
| 238 | /* Ungating Tx only */ |
| 239 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), |
| 240 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, |
| 241 | GFX_TIMEOUT), |
| 242 | /* Ungating Common Lane only */ |
| 243 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), |
| 244 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, |
| 245 | GFX_TIMEOUT), |
| 246 | /* Ungating Display */ |
| 247 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), |
| 248 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, |
| 249 | GFX_TIMEOUT), |
| 250 | REG_SCRIPT_END |
| 251 | }; |
| 252 | |
| 253 | static const struct reg_script gfx_post_vbios_script[] = { |
| 254 | /* Deassert Render Force-Wake */ |
| 255 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), |
| 256 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), |
| 257 | /* Deassert Media Force-Wake */ |
| 258 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), |
| 259 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), |
| 260 | /* Set Lock bits */ |
| 261 | REG_PCI_RMW32(GGC, 0xffffffff, 1), |
| 262 | REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), |
| 263 | REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), |
| 264 | REG_SCRIPT_END |
| 265 | }; |
| 266 | |
| 267 | static inline void gfx_run_script(device_t dev, const struct reg_script *ops) |
| 268 | { |
| 269 | reg_script_run_on_dev(dev, ops); |
| 270 | } |
| 271 | |
| 272 | static void gfx_pre_vbios_init(device_t dev) |
| 273 | { |
| 274 | printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); |
| 275 | gfx_run_script(dev, gpu_pre_vbios_script); |
| 276 | } |
| 277 | |
| 278 | static void gfx_pm_init(device_t dev) |
| 279 | { |
| 280 | printk(BIOS_INFO, "GFX: Power Management Init\n"); |
| 281 | gfx_run_script(dev, gfx_init_script); |
| 282 | |
| 283 | /* Lock power context base */ |
| 284 | gfx_lock_pcbase(dev); |
| 285 | } |
| 286 | |
| 287 | static void gfx_post_vbios_init(device_t dev) |
| 288 | { |
| 289 | printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); |
| 290 | gfx_run_script(dev, gfx_post_vbios_script); |
| 291 | } |
| 292 | |
| 293 | static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz) |
| 294 | { |
| 295 | int divider; |
| 296 | struct resource *res; |
| 297 | |
| 298 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 299 | |
| 300 | if (res == NULL) |
| 301 | return; |
| 302 | |
| 303 | /* Default to 200 Hz if nothing is set. */ |
| 304 | if (req_hz == 0) |
| 305 | req_hz = 200; |
| 306 | |
| 307 | /* Base clock is 25MHz */ |
| 308 | divider = 25 * 1000 * 1000 / (16 * req_hz); |
| 309 | |
| 310 | /* Do not set duty cycle (lower 16 bits). Just set the divider. */ |
| 311 | write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16); |
| 312 | } |
| 313 | |
| 314 | static void gfx_panel_setup(device_t dev) |
| 315 | { |
| 316 | struct soc_intel_baytrail_config *config = dev->chip_info; |
| 317 | struct reg_script gfx_pipea_init[] = { |
| 318 | /* CONTROL */ |
| 319 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), |
| 320 | PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), |
| 321 | /* POWER ON */ |
| 322 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), |
| 323 | (config->gpu_pipea_port_select << 30 | |
| 324 | config->gpu_pipea_power_on_delay << 16 | |
| 325 | config->gpu_pipea_light_on_delay)), |
| 326 | /* POWER OFF */ |
| 327 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), |
| 328 | (config->gpu_pipea_power_off_delay << 16 | |
| 329 | config->gpu_pipea_light_off_delay)), |
| 330 | /* DIVISOR */ |
| 331 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), |
| 332 | ~0x1f, config->gpu_pipea_power_cycle_delay), |
| 333 | REG_SCRIPT_END |
| 334 | }; |
| 335 | struct reg_script gfx_pipeb_init[] = { |
| 336 | /* CONTROL */ |
| 337 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), |
| 338 | PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), |
| 339 | /* POWER ON */ |
| 340 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), |
| 341 | (config->gpu_pipeb_port_select << 30 | |
| 342 | config->gpu_pipeb_power_on_delay << 16 | |
| 343 | config->gpu_pipeb_light_on_delay)), |
| 344 | /* POWER OFF */ |
| 345 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), |
| 346 | (config->gpu_pipeb_power_off_delay << 16 | |
| 347 | config->gpu_pipeb_light_off_delay)), |
| 348 | /* DIVISOR */ |
| 349 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), |
| 350 | ~0x1f, config->gpu_pipeb_power_cycle_delay), |
| 351 | REG_SCRIPT_END |
| 352 | }; |
| 353 | |
| 354 | if (config->gpu_pipea_port_select) { |
| 355 | printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); |
| 356 | reg_script_run_on_dev(dev, gfx_pipea_init); |
| 357 | set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL), |
| 358 | config->gpu_pipea_pwm_freq_hz); |
| 359 | } |
| 360 | |
| 361 | if (config->gpu_pipeb_port_select) { |
| 362 | printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); |
| 363 | reg_script_run_on_dev(dev, gfx_pipeb_init); |
| 364 | set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL), |
| 365 | config->gpu_pipeb_pwm_freq_hz); |
| 366 | } |
| 367 | } |
| 368 | |
| 369 | static void gfx_init(device_t dev) |
| 370 | { |
| 371 | /* Pre VBIOS Init */ |
| 372 | gfx_pre_vbios_init(dev); |
| 373 | |
| 374 | /* Power Management Init */ |
| 375 | gfx_pm_init(dev); |
| 376 | |
| 377 | gfx_panel_setup(dev); |
| 378 | |
| 379 | /* Run VBIOS */ |
| 380 | pci_dev_init(dev); |
| 381 | |
| 382 | /* Post VBIOS Init */ |
| 383 | gfx_post_vbios_init(dev); |
| 384 | } |
| 385 | |
| 386 | static struct device_operations gfx_device_ops = { |
| 387 | .read_resources = pci_dev_read_resources, |
| 388 | .set_resources = pci_dev_set_resources, |
| 389 | .enable_resources = pci_dev_enable_resources, |
| 390 | .init = gfx_init, |
| 391 | .ops_pci = &soc_pci_ops, |
| 392 | }; |
| 393 | |
| 394 | static const struct pci_driver gfx_driver __pci_driver = { |
| 395 | .ops = &gfx_device_ops, |
| 396 | .vendor = PCI_VENDOR_ID_INTEL, |
| 397 | .device = GFX_DEVID, |
| 398 | }; |