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Angel Ponsba38f372020-04-05 15:46:45 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Lee Leahy77ff0b12015-05-05 15:07:29 -07003
Lee Leahy32471722015-04-20 15:20:28 -07004#include "chip.h"
Lee Leahy77ff0b12015-05-05 15:07:29 -07005#include <console/console.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -07006#include <device/device.h>
7#include <device/pci.h>
8#include <device/pci_ids.h>
Matt DeVillier132bbe62017-07-01 13:02:47 -05009#include <drivers/intel/gma/opregion.h>
Matt DeVillier8ff2ecd2020-03-29 16:58:48 -050010#include <drivers/intel/gma/i915.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070011#include <reg_script.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070012#include <soc/gfx.h>
Matt DeVillier132bbe62017-07-01 13:02:47 -050013#include <soc/nvs.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070014#include <soc/pci_devs.h>
15#include <soc/ramstage.h>
16
Lee Leahy77ff0b12015-05-05 15:07:29 -070017static const struct reg_script gpu_pre_vbios_script[] = {
18 /* Make sure GFX is bus master with MMIO access */
19 REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
Lee Leahy77ff0b12015-05-05 15:07:29 -070020 REG_SCRIPT_END
21};
22
23static const struct reg_script gfx_post_vbios_script[] = {
Lee Leahy77ff0b12015-05-05 15:07:29 -070024 /* Set Lock bits */
Angel Ponsaee7ab22020-03-19 00:31:58 +010025 REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK),
Lee Leahy32471722015-04-20 15:20:28 -070026 REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK),
27 REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK),
Lee Leahy77ff0b12015-05-05 15:07:29 -070028 REG_SCRIPT_END
29};
30
Angel Ponsaee7ab22020-03-19 00:31:58 +010031static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)
Lee Leahy77ff0b12015-05-05 15:07:29 -070032{
33 reg_script_run_on_dev(dev, ops);
34}
35
Elyes HAOUASb13fac32018-05-24 22:29:44 +020036static void gfx_pre_vbios_init(struct device *dev)
Lee Leahy77ff0b12015-05-05 15:07:29 -070037{
Angel Ponsaee7ab22020-03-19 00:31:58 +010038 printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
Lee Leahy77ff0b12015-05-05 15:07:29 -070039 printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
40 gfx_run_script(dev, gpu_pre_vbios_script);
41}
42
Elyes HAOUASb13fac32018-05-24 22:29:44 +020043static void gfx_post_vbios_init(struct device *dev)
Lee Leahy77ff0b12015-05-05 15:07:29 -070044{
Angel Ponsaee7ab22020-03-19 00:31:58 +010045 printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
Lee Leahy77ff0b12015-05-05 15:07:29 -070046 printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
47 gfx_run_script(dev, gfx_post_vbios_script);
48}
49
Elyes HAOUASb13fac32018-05-24 22:29:44 +020050static void gfx_init(struct device *dev)
Lee Leahy77ff0b12015-05-05 15:07:29 -070051{
Angel Ponsaee7ab22020-03-19 00:31:58 +010052 printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
Lee Leahy32471722015-04-20 15:20:28 -070053
Julius Wernercd49cce2019-03-05 16:53:33 -080054 if (!CONFIG(RUN_FSP_GOP)) {
Matt DeVilliera9492a62018-06-20 00:40:48 -050055 /* Pre VBIOS Init */
56 gfx_pre_vbios_init(dev);
Lee Leahy77ff0b12015-05-05 15:07:29 -070057
Matt DeVilliera9492a62018-06-20 00:40:48 -050058 /* Run VBIOS */
59 pci_dev_init(dev);
Lee Leahy77ff0b12015-05-05 15:07:29 -070060
Matt DeVilliera9492a62018-06-20 00:40:48 -050061 /* Post VBIOS Init */
62 gfx_post_vbios_init(dev);
63 }
Matt DeVillier132bbe62017-07-01 13:02:47 -050064 intel_gma_restore_opregion();
65}
66
67uintptr_t gma_get_gnvs_aslb(const void *gnvs)
68{
69 const global_nvs_t *gnvs_ptr = gnvs;
70 return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
71}
72
73void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
74{
75 global_nvs_t *gnvs_ptr = gnvs;
76 if (gnvs_ptr)
77 gnvs_ptr->aslb = aslb;
Lee Leahy77ff0b12015-05-05 15:07:29 -070078}
79
Matt DeVillier8ff2ecd2020-03-29 16:58:48 -050080static void gma_generate_ssdt(struct device *dev)
81{
82 const struct soc_intel_braswell_config *chip = dev->chip_info;
83
84 drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
85}
86
Lee Leahy77ff0b12015-05-05 15:07:29 -070087static struct device_operations gfx_device_ops = {
Nico Huber1ef80142015-11-05 23:27:06 +010088 .read_resources = pci_dev_read_resources,
Lee Leahy77ff0b12015-05-05 15:07:29 -070089 .set_resources = pci_dev_set_resources,
90 .enable_resources = pci_dev_enable_resources,
91 .init = gfx_init,
92 .ops_pci = &soc_pci_ops,
Matt DeVillier8ff2ecd2020-03-29 16:58:48 -050093 .acpi_fill_ssdt = gma_generate_ssdt,
Lee Leahy77ff0b12015-05-05 15:07:29 -070094};
95
96static const struct pci_driver gfx_driver __pci_driver = {
97 .ops = &gfx_device_ops,
98 .vendor = PCI_VENDOR_ID_INTEL,
99 .device = GFX_DEVID,
100};