Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 2 | |
Srinidhi N Kaushik | 4af0adb | 2020-02-29 00:32:23 -0800 | [diff] [blame] | 3 | #include <assert.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
Shreesh Chhabbi | fbad99f | 2021-01-20 09:07:25 -0800 | [diff] [blame] | 6 | #include <arch/pci_io_cfg.h> |
| 7 | #include <device/pci_ops.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 8 | #include <device/pci.h> |
Shreesh Chhabbi | fbad99f | 2021-01-20 09:07:25 -0800 | [diff] [blame] | 9 | #include <device/pci_ids.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 10 | #include <fsp/api.h> |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 11 | #include <fsp/ppi/mp_service_ppi.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 12 | #include <fsp/util.h> |
Jamie Ryu | 02a1b33 | 2020-06-11 01:57:13 -0700 | [diff] [blame] | 13 | #include <intelblocks/cse.h> |
Aamir Bohra | 86da00d | 2019-12-06 19:57:36 +0530 | [diff] [blame] | 14 | #include <intelblocks/lpss.h> |
John Zhao | bd615d6 | 2020-07-27 13:22:11 -0700 | [diff] [blame] | 15 | #include <intelblocks/mp_init.h> |
Jamie Ryu | 5b7daa2 | 2020-08-18 18:54:49 -0700 | [diff] [blame] | 16 | #include <intelblocks/pmclib.h> |
Tim Wawrzynczak | eb6ebc0 | 2021-03-22 16:39:57 -0600 | [diff] [blame] | 17 | #include <intelblocks/tcss.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 18 | #include <intelblocks/xdci.h> |
Wonkyu Kim | 3ba64ca | 2020-03-20 12:17:14 -0700 | [diff] [blame] | 19 | #include <intelpch/lockdown.h> |
Jamie Ryu | 02a1b33 | 2020-06-11 01:57:13 -0700 | [diff] [blame] | 20 | #include <security/vboot/vboot_common.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 21 | #include <soc/gpio_soc_defs.h> |
| 22 | #include <soc/intel/common/vbt.h> |
| 23 | #include <soc/pci_devs.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 24 | #include <soc/ramstage.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 25 | #include <soc/soc_chip.h> |
Tim Wawrzynczak | 59a621a | 2021-03-22 10:43:42 -0600 | [diff] [blame] | 26 | #include <soc/tcss.h> |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 27 | #include <string.h> |
| 28 | |
Wonkyu Kim | 4cabf78 | 2020-05-20 13:09:39 -0700 | [diff] [blame] | 29 | /* THC assignment definition */ |
| 30 | #define THC_NONE 0 |
| 31 | #define THC_0 1 |
| 32 | #define THC_1 2 |
| 33 | |
Shaunak Saha | 1a8949c | 2020-06-08 18:59:47 -0700 | [diff] [blame] | 34 | /* SATA DEVSLP idle timeout default values */ |
| 35 | #define DEF_DMVAL 15 |
| 36 | #define DEF_DITOVAL 625 |
| 37 | |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 38 | /* |
Nick Vaccaro | 202b189 | 2021-02-22 14:26:13 -0800 | [diff] [blame] | 39 | * ME End of Post configuration |
| 40 | * 0 - Disable EOP. |
| 41 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 42 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 43 | */ |
| 44 | enum { |
| 45 | EOP_DISABLE, |
| 46 | EOP_PEI, |
| 47 | EOP_DXE, |
| 48 | } EndOfPost; |
| 49 | |
| 50 | /* |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 51 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 52 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 53 | * In order to ensure that mainboard setting does not disable L1 substates |
| 54 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 55 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 56 | * value is set in fsp_params. |
| 57 | * 0: Use FSP UPD default |
| 58 | * 1: Disable L1 substates |
| 59 | * 2: Use L1.1 |
| 60 | * 3: Use L1.2 (FSP UPD default) |
| 61 | */ |
| 62 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 63 | { |
| 64 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 65 | ctl = L1_SS_L1_2; |
| 66 | return ctl - 1; |
| 67 | } |
| 68 | |
Shreesh Chhabbi | fbad99f | 2021-01-20 09:07:25 -0800 | [diff] [blame] | 69 | /* Function returns true if the platform is TGL-UP3 */ |
| 70 | static bool platform_is_up3(void) |
| 71 | { |
| 72 | const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 73 | u32 cpu_id = cpu_get_cpuid(); |
| 74 | uint16_t mchid = pci_read_config16(dev, PCI_DEVICE_ID); |
| 75 | |
| 76 | if ((cpu_id != CPUID_TIGERLAKE_A0) && (cpu_id != CPUID_TIGERLAKE_B0)) |
| 77 | return false; |
| 78 | |
| 79 | return ((mchid == PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2) || |
| 80 | (mchid == PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2)); |
| 81 | } |
| 82 | |
| 83 | static int get_disable_mask(struct soc_intel_tigerlake_config *config) |
| 84 | { |
| 85 | int disable_mask; |
| 86 | |
| 87 | /* Disable any sub-states requested by mainboard */ |
| 88 | disable_mask = config->LpmStateDisableMask; |
| 89 | |
| 90 | /* UP3 does not support S0i2.2/S0i3.3/S0i3.4 */ |
| 91 | if (platform_is_up3()) |
| 92 | disable_mask |= LPM_S0i3_3 | LPM_S0i3_4 | LPM_S0i2_2; |
| 93 | |
| 94 | /* If external bypass is not used, S0i3 isn't recommended. */ |
| 95 | if (config->external_bypass == false) |
| 96 | disable_mask |= LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4; |
| 97 | |
| 98 | /* If external clock gating is not implemented, S0i3.4 isn't recommended. */ |
| 99 | if (config->external_clk_gated == false) |
| 100 | disable_mask |= LPM_S0i3_4; |
| 101 | |
| 102 | /* |
| 103 | * If external phy gating is not implemented, |
| 104 | * S0i3.3/S0i3.4/S0i2.2 are not recommended. |
| 105 | */ |
| 106 | if (config->external_phy_gated == false) |
| 107 | disable_mask |= LPM_S0i3_3 | LPM_S0i3_4 | LPM_S0i2_2; |
| 108 | |
| 109 | /* If CNVi or ISH is used, S0i3.2/S0i3.3/S0i3.4 cannot be achieved. */ |
Cliff Huang | b34be4d | 2021-02-04 15:37:24 -0800 | [diff] [blame] | 110 | if (is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI)) || |
Shreesh Chhabbi | fbad99f | 2021-01-20 09:07:25 -0800 | [diff] [blame] | 111 | is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_ISH))) |
| 112 | disable_mask |= LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4; |
| 113 | |
| 114 | return disable_mask; |
| 115 | } |
| 116 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 117 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 118 | { |
| 119 | const struct soc_intel_tigerlake_config *config; |
| 120 | config = config_of_soc(); |
| 121 | |
| 122 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
| 123 | params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
| 124 | |
| 125 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
| 126 | params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 127 | params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 128 | params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
| 129 | } |
| 130 | |
| 131 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
| 132 | params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
| 133 | } |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 134 | |
Jes Klinke | 476ca3a | 2020-08-28 13:44:21 -0700 | [diff] [blame] | 135 | __weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config) |
| 136 | { |
| 137 | /* Override settings per board. */ |
| 138 | } |
| 139 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 140 | /* UPD parameters to be initialized before SiliconInit */ |
| 141 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 142 | { |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 143 | int i; |
John Zhao | bd615d6 | 2020-07-27 13:22:11 -0700 | [diff] [blame] | 144 | uint32_t cpu_id; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 145 | FSP_S_CONFIG *params = &supd->FspsConfig; |
| 146 | |
| 147 | struct device *dev; |
| 148 | struct soc_intel_tigerlake_config *config; |
| 149 | config = config_of_soc(); |
Jes Klinke | 476ca3a | 2020-08-28 13:44:21 -0700 | [diff] [blame] | 150 | mainboard_update_soc_chip_config(config); |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 151 | |
| 152 | /* Parse device tree and enable/disable Serial I/O devices */ |
| 153 | parse_devicetree(params); |
| 154 | |
| 155 | /* Load VBT before devicetree-specific config. */ |
| 156 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 157 | |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 158 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 159 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Felix Singer | 5c10704 | 2020-07-26 09:22:42 +0200 | [diff] [blame] | 160 | params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 161 | |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 162 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
Subrata Banik | 6362de3 | 2020-07-30 11:31:55 +0530 | [diff] [blame] | 163 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 164 | params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 165 | |
John Zhao | 8aac881 | 2020-05-16 13:06:25 -0700 | [diff] [blame] | 166 | /* D3Hot and D3Cold for TCSS */ |
John Zhao | bd615d6 | 2020-07-27 13:22:11 -0700 | [diff] [blame] | 167 | params->D3HotEnable = !config->TcssD3HotDisable; |
| 168 | cpu_id = cpu_get_cpuid(); |
| 169 | if (cpu_id == CPUID_TIGERLAKE_A0) |
| 170 | params->D3ColdEnable = 0; |
| 171 | else |
| 172 | params->D3ColdEnable = !config->TcssD3ColdDisable; |
John Zhao | 8aac881 | 2020-05-16 13:06:25 -0700 | [diff] [blame] | 173 | |
Brandon Breitenstein | bf50c31 | 2020-12-21 14:55:38 -0800 | [diff] [blame] | 174 | params->UsbTcPortEn = config->UsbTcPortEn; |
Brandon Breitenstein | fc93237 | 2020-03-11 14:07:23 -0700 | [diff] [blame] | 175 | params->TcssAuxOri = config->TcssAuxOri; |
Tim Wawrzynczak | 59a621a | 2021-03-22 10:43:42 -0600 | [diff] [blame] | 176 | |
| 177 | /* Explicitly clear this field to avoid using defaults */ |
| 178 | memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg)); |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 179 | |
John Zhao | 92a3a30 | 2020-06-03 13:06:24 -0700 | [diff] [blame] | 180 | /* |
| 181 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 182 | * evaluate this UPD value and skip sending command. There will be no |
| 183 | * delay for command completion. |
| 184 | */ |
| 185 | params->ITbtConnectTopologyTimeoutInMs = 0; |
| 186 | |
Srinidhi N Kaushik | 44509d8 | 2021-01-08 10:01:25 -0800 | [diff] [blame] | 187 | /* Disable TcColdOnUsbConnect */ |
| 188 | params->DisableTccoldOnUsbConnected = 1; |
| 189 | |
Wonkyu Kim | 3ba64ca | 2020-03-20 12:17:14 -0700 | [diff] [blame] | 190 | /* Chipset Lockdown */ |
| 191 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
| 192 | params->PchLockDownGlobalSmi = 0; |
| 193 | params->PchLockDownBiosInterface = 0; |
| 194 | params->PchUnlockGpioPads = 1; |
| 195 | params->RtcMemoryLock = 0; |
| 196 | } else { |
| 197 | params->PchLockDownGlobalSmi = 1; |
| 198 | params->PchLockDownBiosInterface = 1; |
| 199 | params->PchUnlockGpioPads = 0; |
| 200 | params->RtcMemoryLock = 1; |
| 201 | } |
| 202 | |
Nick Vaccaro | 202b189 | 2021-02-22 14:26:13 -0800 | [diff] [blame] | 203 | /* Enable End of Post in PEI phase */ |
| 204 | params->EndOfPostMessage = EOP_PEI; |
| 205 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 206 | /* USB */ |
| 207 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 208 | params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 209 | params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 210 | params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 211 | params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 212 | params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 213 | |
| 214 | if (config->usb2_ports[i].enable) |
| 215 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 216 | else |
| 217 | params->Usb2OverCurrentPin[i] = 0xff; |
John Zhao | 4ead6b33 | 2021-01-01 14:19:36 -0800 | [diff] [blame] | 218 | |
| 219 | if (config->usb2_ports[i].type_c) |
| 220 | params->PortResetMessageEnable[i] = 1; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 224 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 225 | if (config->usb3_ports[i].enable) { |
| 226 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 227 | } else { |
| 228 | params->Usb3OverCurrentPin[i] = 0xff; |
| 229 | } |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 230 | if (config->usb3_ports[i].tx_de_emp) { |
| 231 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 232 | params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 233 | } |
| 234 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 235 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 236 | params->Usb3HsioTxDownscaleAmp[i] = |
| 237 | config->usb3_ports[i].tx_downscale_amp; |
| 238 | } |
| 239 | } |
| 240 | |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 241 | /* RP Configs */ |
Wonkyu Kim | 5943117 | 2020-04-07 20:45:28 -0700 | [diff] [blame] | 242 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 243 | params->PcieRpL1Substates[i] = |
| 244 | get_l1_substate_control(config->PcieRpL1Substates[i]); |
Wonkyu Kim | 5943117 | 2020-04-07 20:45:28 -0700 | [diff] [blame] | 245 | params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; |
| 246 | params->PcieRpAdvancedErrorReporting[i] = |
| 247 | config->PcieRpAdvancedErrorReporting[i]; |
Wonkyu Kim | c66c153 | 2020-05-27 13:34:04 -0700 | [diff] [blame] | 248 | params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; |
Duncan Laurie | 17e905ac | 2020-10-27 17:57:13 -0700 | [diff] [blame] | 249 | params->PciePtm[i] = config->PciePtm[i]; |
Wonkyu Kim | 5943117 | 2020-04-07 20:45:28 -0700 | [diff] [blame] | 250 | } |
Meera Ravindranath | 0d6cc22 | 2020-04-29 12:19:33 +0530 | [diff] [blame] | 251 | |
| 252 | /* Enable ClkReqDetect for enabled port */ |
| 253 | memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, |
| 254 | sizeof(config->PcieRpClkReqDetect)); |
| 255 | |
Nick Vaccaro | 4b3e06e | 2021-05-11 16:39:32 -0700 | [diff] [blame] | 256 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 257 | if (config->tcss_ports[i].enable) |
| 258 | params->CpuUsb3OverCurrentPin[i] = |
| 259 | config->tcss_ports[i].ocpin; |
| 260 | } |
| 261 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 262 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 263 | dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); |
John Zhao | ad64781 | 2020-03-03 10:03:57 -0800 | [diff] [blame] | 264 | if (dev) { |
| 265 | if (!xdci_can_enable()) |
| 266 | dev->enabled = 0; |
| 267 | params->XdciEnable = dev->enabled; |
| 268 | } else { |
| 269 | params->XdciEnable = 0; |
| 270 | } |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 271 | |
| 272 | /* PCH UART selection for FSP Debug */ |
| 273 | params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
Srinidhi N Kaushik | 4af0adb | 2020-02-29 00:32:23 -0800 | [diff] [blame] | 274 | ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 275 | params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 276 | |
Wonkyu Kim | 815d96a | 2020-01-21 21:51:19 -0800 | [diff] [blame] | 277 | /* SATA */ |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 278 | dev = pcidev_path_on_root(PCH_DEVFN_SATA); |
Felix Singer | 5c10704 | 2020-07-26 09:22:42 +0200 | [diff] [blame] | 279 | params->SataEnable = is_dev_enabled(dev); |
| 280 | if (params->SataEnable) { |
Wonkyu Kim | 815d96a | 2020-01-21 21:51:19 -0800 | [diff] [blame] | 281 | params->SataMode = config->SataMode; |
| 282 | params->SataSalpSupport = config->SataSalpSupport; |
| 283 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 284 | sizeof(params->SataPortsEnable)); |
| 285 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 286 | sizeof(params->SataPortsDevSlp)); |
| 287 | } |
| 288 | |
Jes Klinke | 6fd87ff | 2020-08-10 13:30:40 -0700 | [diff] [blame] | 289 | /* S0iX: Selectively enable individual sub-states, |
| 290 | * by default all are enabled. |
| 291 | * |
| 292 | * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, |
| 293 | * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4 |
| 294 | */ |
Shreesh Chhabbi | fbad99f | 2021-01-20 09:07:25 -0800 | [diff] [blame] | 295 | params->LpmStateEnableMask = LPM_S0iX_ALL & ~get_disable_mask(config); |
Jes Klinke | 6fd87ff | 2020-08-10 13:30:40 -0700 | [diff] [blame] | 296 | |
Shaunak Saha | 32b8a51 | 2020-03-31 22:56:13 -0700 | [diff] [blame] | 297 | /* |
| 298 | * Power Optimizer for DMI and SATA. |
| 299 | * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. |
| 300 | * Boards not needing the optimizers explicitly disables them by setting |
| 301 | * these disable variables to 1 in devicetree overrides. |
| 302 | */ |
| 303 | params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); |
| 304 | params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
| 305 | |
Shaunak Saha | 1a8949c | 2020-06-08 18:59:47 -0700 | [diff] [blame] | 306 | /* |
| 307 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 308 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 309 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 310 | * The default values can be changed from devicetree. |
| 311 | */ |
| 312 | for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { |
| 313 | if (config->SataPortsEnableDitoConfig[i]) { |
| 314 | if (config->SataPortsDmVal[i]) |
| 315 | params->SataPortsDmVal[i] = config->SataPortsDmVal[i]; |
| 316 | else |
| 317 | params->SataPortsDmVal[i] = DEF_DMVAL; |
| 318 | |
| 319 | if (config->SataPortsDitoVal[i]) |
| 320 | params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; |
| 321 | else |
| 322 | params->SataPortsDitoVal[i] = DEF_DITOVAL; |
| 323 | } |
| 324 | } |
| 325 | |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 326 | params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; |
Shaunak Saha | 82d5123 | 2021-02-17 23:26:43 -0800 | [diff] [blame] | 327 | params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable; |
| 328 | params->SlowSlewRate[0] = config->SlowSlewRate; |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 329 | |
Sumeet R Pawnikar | 7d6bc60 | 2020-05-08 19:22:07 +0530 | [diff] [blame] | 330 | /* Enable TCPU for processor thermal control */ |
| 331 | params->Device4Enable = config->Device4Enable; |
| 332 | |
Sumeet R Pawnikar | 6caa476 | 2020-06-18 16:50:58 +0530 | [diff] [blame] | 333 | /* Set TccActivationOffset */ |
| 334 | params->TccActivationOffset = config->tcc_offset; |
| 335 | |
Wonkyu Kim | b3fa6a0 | 2020-02-27 15:54:56 -0800 | [diff] [blame] | 336 | /* LAN */ |
Wonkyu Kim | 82e0a81 | 2020-04-13 13:26:05 -0700 | [diff] [blame] | 337 | dev = pcidev_path_on_root(PCH_DEVFN_GBE); |
Felix Singer | 5c10704 | 2020-07-26 09:22:42 +0200 | [diff] [blame] | 338 | params->PchLanEnable = is_dev_enabled(dev); |
Wonkyu Kim | b3fa6a0 | 2020-02-27 15:54:56 -0800 | [diff] [blame] | 339 | |
Srinidhi N Kaushik | 8488853 | 2020-03-05 00:54:02 -0800 | [diff] [blame] | 340 | /* CNVi */ |
Srinidhi N Kaushik | a6bff2d | 2020-03-12 01:15:43 -0700 | [diff] [blame] | 341 | dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); |
Felix Singer | 5c10704 | 2020-07-26 09:22:42 +0200 | [diff] [blame] | 342 | params->CnviMode = is_dev_enabled(dev); |
Cliff Huang | b34be4d | 2021-02-04 15:37:24 -0800 | [diff] [blame] | 343 | params->CnviBtCore = config->CnviBtCore; |
John Zhao | c16fc8a | 2020-09-21 13:10:11 -0700 | [diff] [blame] | 344 | params->CnviBtAudioOffload = config->CnviBtAudioOffload; |
Cliff Huang | b34be4d | 2021-02-04 15:37:24 -0800 | [diff] [blame] | 345 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
| 346 | assert(params->CnviMode || !params->CnviBtCore); |
| 347 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
| 348 | assert(params->CnviBtCore || !params->CnviBtAudioOffload); |
John Zhao | c16fc8a | 2020-09-21 13:10:11 -0700 | [diff] [blame] | 349 | |
Wonkyu Kim | 165efa1 | 2020-05-05 09:10:13 -0700 | [diff] [blame] | 350 | /* VMD */ |
| 351 | dev = pcidev_path_on_root(SA_DEVFN_VMD); |
Felix Singer | 5c10704 | 2020-07-26 09:22:42 +0200 | [diff] [blame] | 352 | params->VmdEnable = is_dev_enabled(dev); |
Wonkyu Kim | 165efa1 | 2020-05-05 09:10:13 -0700 | [diff] [blame] | 353 | |
Wonkyu Kim | 4cabf78 | 2020-05-20 13:09:39 -0700 | [diff] [blame] | 354 | /* THC */ |
| 355 | dev = pcidev_path_on_root(PCH_DEVFN_THC0); |
Felix Singer | 5c10704 | 2020-07-26 09:22:42 +0200 | [diff] [blame] | 356 | params->ThcPort0Assignment = is_dev_enabled(dev) ? THC_0 : THC_NONE; |
Wonkyu Kim | 4cabf78 | 2020-05-20 13:09:39 -0700 | [diff] [blame] | 357 | |
| 358 | dev = pcidev_path_on_root(PCH_DEVFN_THC1); |
Felix Singer | 5c10704 | 2020-07-26 09:22:42 +0200 | [diff] [blame] | 359 | params->ThcPort1Assignment = is_dev_enabled(dev) ? THC_1 : THC_NONE; |
Wonkyu Kim | 4cabf78 | 2020-05-20 13:09:39 -0700 | [diff] [blame] | 360 | |
Subrata Banik | 1bfd56cb | 2020-02-24 15:14:22 +0530 | [diff] [blame] | 361 | /* Legacy 8254 timer support */ |
Martin Roth | c25c1eb | 2020-07-24 12:26:21 -0600 | [diff] [blame] | 362 | params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); |
| 363 | params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); |
Subrata Banik | 1bfd56cb | 2020-02-24 15:14:22 +0530 | [diff] [blame] | 364 | |
Wonkyu Kim | 2b4ded0 | 2020-03-03 01:43:45 -0800 | [diff] [blame] | 365 | /* Enable Hybrid storage auto detection */ |
Jamie Ryu | 02a1b33 | 2020-06-11 01:57:13 -0700 | [diff] [blame] | 366 | if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite() |
| 367 | && vboot_recovery_mode_enabled() && !cse_is_hfs1_com_normal()) { |
| 368 | /* |
| 369 | * CSE Lite SKU does not support hybrid storage dynamic configuration |
| 370 | * in CSE RO boot, and FSP does not allow to send the strap override |
| 371 | * HECI commands if CSE is not in normal mode; hence, hybrid storage |
| 372 | * mode is disabled on CSE RO boot in recovery boot mode. |
| 373 | */ |
| 374 | printk(BIOS_INFO, "cse_lite: CSE RO boot. HybridStorageMode disabled\n"); |
| 375 | params->HybridStorageMode = 0; |
| 376 | } else { |
| 377 | params->HybridStorageMode = config->HybridStorageMode; |
| 378 | } |
Wonkyu Kim | 2b4ded0 | 2020-03-03 01:43:45 -0800 | [diff] [blame] | 379 | |
Brandon Breitenstein | 1163745 | 2020-02-06 14:20:57 -0800 | [diff] [blame] | 380 | /* USB4/TBT */ |
| 381 | for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { |
| 382 | dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); |
| 383 | if (dev) |
| 384 | params->ITbtPcieRootPortEn[i] = dev->enabled; |
| 385 | else |
| 386 | params->ITbtPcieRootPortEn[i] = 0; |
| 387 | } |
| 388 | |
Venkata Krishna Nimmagadda | e18f719 | 2020-05-15 00:13:40 -0700 | [diff] [blame] | 389 | /* PCH FIVR settings override */ |
| 390 | if (config->ext_fivr_settings.configure_ext_fivr) { |
| 391 | params->PchFivrExtV1p05RailEnabledStates = |
| 392 | config->ext_fivr_settings.v1p05_enable_bitmap; |
| 393 | |
| 394 | params->PchFivrExtV1p05RailSupportedVoltageStates = |
| 395 | config->ext_fivr_settings.v1p05_supported_voltage_bitmap; |
| 396 | |
| 397 | params->PchFivrExtVnnRailEnabledStates = |
| 398 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 399 | |
| 400 | params->PchFivrExtVnnRailSupportedVoltageStates = |
| 401 | config->ext_fivr_settings.vnn_supported_voltage_bitmap; |
| 402 | |
| 403 | /* convert mV to number of 2.5 mV increments */ |
| 404 | params->PchFivrExtVnnRailSxVoltage = |
| 405 | (config->ext_fivr_settings.vnn_sx_voltage_mv * 10) / 25; |
| 406 | |
| 407 | params->PchFivrExtV1p05RailIccMaximum = |
| 408 | config->ext_fivr_settings.v1p05_icc_max_ma; |
| 409 | |
| 410 | } |
| 411 | |
Jamie Ryu | 5b7daa2 | 2020-08-18 18:54:49 -0700 | [diff] [blame] | 412 | /* Apply minimum assertion width settings if non-zero */ |
| 413 | if (config->PchPmSlpS3MinAssert) |
| 414 | params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; |
| 415 | if (config->PchPmSlpS4MinAssert) |
| 416 | params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert; |
| 417 | if (config->PchPmSlpSusMinAssert) |
| 418 | params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert; |
| 419 | if (config->PchPmSlpAMinAssert) |
| 420 | params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert; |
| 421 | |
| 422 | /* Set Power Cycle Duration */ |
| 423 | if (config->PchPmPwrCycDur) |
| 424 | params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert, |
| 425 | config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, |
| 426 | config->PchPmPwrCycDur); |
| 427 | |
Subrata Banik | b622d4b | 2020-05-26 18:33:22 +0530 | [diff] [blame] | 428 | /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ |
| 429 | params->EnableMultiPhaseSiliconInit = 1; |
Ravi Sarawadi | d83e24d | 2020-10-14 16:30:38 -0700 | [diff] [blame] | 430 | |
| 431 | /* Disable C1 C-state Demotion */ |
| 432 | params->C1StateAutoDemotion = 0; |
| 433 | |
Derek Huang | 8056187 | 2021-03-15 12:11:19 +0800 | [diff] [blame] | 434 | /* USB2 Phy Sus power gating setting override */ |
| 435 | params->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable; |
| 436 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 437 | mainboard_silicon_init_params(params); |
| 438 | } |
| 439 | |
Subrata Banik | b622d4b | 2020-05-26 18:33:22 +0530 | [diff] [blame] | 440 | /* |
| 441 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 442 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 443 | * Phase | FSP return point | Purpose |
| 444 | * ------- + ------------------------------------------------ + ------------------------------- |
| 445 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 446 | */ |
| 447 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 448 | { |
| 449 | switch (phase_index) { |
| 450 | case 1: |
| 451 | /* TCSS specific initialization here */ |
Brandon Breitenstein | 99b38a9 | 2019-12-19 23:12:58 -0800 | [diff] [blame] | 452 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 453 | __FILE__, __func__); |
Tim Wawrzynczak | eb6ebc0 | 2021-03-22 16:39:57 -0600 | [diff] [blame] | 454 | |
Tim Wawrzynczak | 59a621a | 2021-03-22 10:43:42 -0600 | [diff] [blame] | 455 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 456 | const config_t *config = config_of_soc(); |
| 457 | tcss_configure(config->typec_aux_bias_pads); |
| 458 | } |
Subrata Banik | b622d4b | 2020-05-26 18:33:22 +0530 | [diff] [blame] | 459 | break; |
| 460 | default: |
| 461 | break; |
| 462 | } |
| 463 | } |
| 464 | |
Srinidhi N Kaushik | d801b1f | 2019-12-27 13:28:01 -0800 | [diff] [blame] | 465 | /* Mainboard GPIO Configuration */ |
| 466 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 467 | { |
| 468 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 469 | } |