Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 2 | |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 3 | #include <timestamp.h> |
| 4 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 6 | #include <cbmem.h> |
Elyes HAOUAS | 363b771 | 2019-04-28 18:07:02 +0200 | [diff] [blame] | 7 | #include <cf9_reset.h> |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 8 | #include <romstage_handoff.h> |
| 9 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Rudolph | 425e75a | 2019-03-24 15:06:17 +0100 | [diff] [blame] | 10 | #include <southbridge/intel/common/pmclib.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 11 | #include <arch/romstage.h> |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 12 | #include "raminit.h" |
| 13 | #include "pineview.h" |
| 14 | |
| 15 | static void rcba_config(void) |
| 16 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 17 | /* Set up Virtual Channel 0 */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 18 | RCBA32(0x0014) = 0x80000001; |
| 19 | RCBA32(0x001c) = 0x03128010; |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 20 | } |
| 21 | |
| 22 | __weak void mb_pirq_setup(void) |
| 23 | { |
| 24 | } |
| 25 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 26 | /* The romstage entry point for this platform is not mainboard-specific, hence the name. */ |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 27 | void mainboard_romstage_entry(void) |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 28 | { |
| 29 | u8 spd_addrmap[4] = {}; |
| 30 | int boot_path, cbmem_was_initted; |
| 31 | int s3resume = 0; |
| 32 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 33 | /* Do some early chipset init, necessary for RAM init to work */ |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 34 | i82801gx_early_init(); |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 35 | pineview_early_init(); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 36 | |
| 37 | post_code(0x30); |
| 38 | |
| 39 | s3resume = southbridge_detect_s3_resume(); |
| 40 | |
| 41 | if (s3resume) { |
| 42 | boot_path = BOOT_PATH_RESUME; |
| 43 | } else { |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 44 | if (mchbar_read32(PMSTS) & (1 << 8)) /* HOT RESET */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 45 | boot_path = BOOT_PATH_RESET; |
| 46 | else |
| 47 | boot_path = BOOT_PATH_NORMAL; |
| 48 | } |
| 49 | |
| 50 | get_mb_spd_addrmap(&spd_addrmap[0]); |
| 51 | |
| 52 | printk(BIOS_DEBUG, "Initializing memory\n"); |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 53 | timestamp_add_now(TS_INITRAM_START); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 54 | sdram_initialize(boot_path, spd_addrmap); |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 55 | timestamp_add_now(TS_INITRAM_END); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 56 | printk(BIOS_DEBUG, "Memory initialized\n"); |
| 57 | |
| 58 | post_code(0x31); |
| 59 | |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 60 | mb_pirq_setup(); |
| 61 | |
| 62 | rcba_config(); |
| 63 | |
| 64 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 65 | |
| 66 | if (!cbmem_was_initted && s3resume) { |
| 67 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | 363b771 | 2019-04-28 18:07:02 +0200 | [diff] [blame] | 68 | system_reset(); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | romstage_handoff_init(s3resume); |
| 72 | } |