| Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | /* Platform has no romstage entry point under mainboard directory, |
| 17 | * so this one is named with prefix mainboard. |
| 18 | */ |
| 19 | |
| 20 | #include <lib.h> |
| 21 | #include <timestamp.h> |
| 22 | #include <console/console.h> |
| 23 | #include <cbmem.h> |
| 24 | #include <romstage_handoff.h> |
| 25 | #include <southbridge/intel/i82801gx/i82801gx.h> |
| 26 | #include <southbridge/intel/common/gpio.h> |
| 27 | #include <cpu/intel/romstage.h> |
| 28 | #include <cpu/x86/bist.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include "raminit.h" |
| 31 | #include "pineview.h" |
| 32 | |
| 33 | static void rcba_config(void) |
| 34 | { |
| 35 | /* Set up virtual channel 0 */ |
| 36 | RCBA32(0x0014) = 0x80000001; |
| 37 | RCBA32(0x001c) = 0x03128010; |
| 38 | |
| 39 | /* Enable IOAPIC */ |
| 40 | RCBA8(OIC) = 0x03; |
| 41 | } |
| 42 | |
| 43 | __weak void mb_pirq_setup(void) |
| 44 | { |
| 45 | } |
| 46 | |
| 47 | #define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0) |
| 48 | |
| 49 | void mainboard_romstage_entry(unsigned long bist) |
| 50 | { |
| 51 | u8 spd_addrmap[4] = {}; |
| 52 | int boot_path, cbmem_was_initted; |
| 53 | int s3resume = 0; |
| 54 | |
| 55 | if (bist == 0) |
| 56 | enable_lapic(); |
| 57 | |
| 58 | /* Disable watchdog timer */ |
| 59 | RCBA32(GCS) = RCBA32(GCS) | 0x20; |
| 60 | |
| 61 | /* Enable GPIOs */ |
| 62 | pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); |
| 63 | pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); |
| 64 | |
| 65 | setup_pch_gpios(&mainboard_gpio_map); |
| 66 | |
| 67 | mb_enable_lpc(); // nm10_enable_lpc |
| 68 | |
| 69 | /* Initialize console device(s) */ |
| 70 | console_init(); |
| 71 | |
| 72 | /* Halt if there was a built in self test failure */ |
| 73 | report_bist_failure(bist); |
| 74 | |
| 75 | enable_smbus(); |
| 76 | |
| 77 | /* Perform some early chipset initialization required |
| 78 | * before RAM initialization can work |
| 79 | */ |
| 80 | pineview_early_initialization(); |
| 81 | |
| 82 | post_code(0x30); |
| 83 | |
| 84 | s3resume = southbridge_detect_s3_resume(); |
| 85 | |
| 86 | if (s3resume) { |
| 87 | boot_path = BOOT_PATH_RESUME; |
| 88 | } else { |
| 89 | if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */ |
| 90 | boot_path = BOOT_PATH_RESET; |
| 91 | else |
| 92 | boot_path = BOOT_PATH_NORMAL; |
| 93 | } |
| 94 | |
| 95 | get_mb_spd_addrmap(&spd_addrmap[0]); |
| 96 | |
| 97 | printk(BIOS_DEBUG, "Initializing memory\n"); |
| 98 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 99 | sdram_initialize(boot_path, spd_addrmap); |
| 100 | timestamp_add_now(TS_AFTER_INITRAM); |
| 101 | printk(BIOS_DEBUG, "Memory initialized\n"); |
| 102 | |
| 103 | post_code(0x31); |
| 104 | |
| 105 | quick_ram_check(); |
| 106 | |
| 107 | mb_pirq_setup(); |
| 108 | |
| 109 | rcba_config(); |
| 110 | |
| 111 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 112 | |
| 113 | if (!cbmem_was_initted && s3resume) { |
| 114 | /* Failed S3 resume, reset to come up cleanly */ |
| 115 | outb(0x6, 0xcf9); |
| 116 | halt(); |
| 117 | } |
| 118 | |
| 119 | romstage_handoff_init(s3resume); |
| 120 | } |