Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 2 | |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 3 | #include <timestamp.h> |
| 4 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 6 | #include <cbmem.h> |
Elyes HAOUAS | 363b771 | 2019-04-28 18:07:02 +0200 | [diff] [blame] | 7 | #include <cf9_reset.h> |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 8 | #include <romstage_handoff.h> |
| 9 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Rudolph | 425e75a | 2019-03-24 15:06:17 +0100 | [diff] [blame] | 10 | #include <southbridge/intel/common/pmclib.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 11 | #include <arch/romstage.h> |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 12 | #include <cpu/x86/lapic.h> |
| 13 | #include "raminit.h" |
| 14 | #include "pineview.h" |
| 15 | |
| 16 | static void rcba_config(void) |
| 17 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 18 | /* Set up Virtual Channel 0 */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 19 | RCBA32(0x0014) = 0x80000001; |
| 20 | RCBA32(0x001c) = 0x03128010; |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 21 | } |
| 22 | |
| 23 | __weak void mb_pirq_setup(void) |
| 24 | { |
| 25 | } |
| 26 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 27 | /* The romstage entry point for this platform is not mainboard-specific, hence the name. */ |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 28 | void mainboard_romstage_entry(void) |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 29 | { |
| 30 | u8 spd_addrmap[4] = {}; |
| 31 | int boot_path, cbmem_was_initted; |
| 32 | int s3resume = 0; |
| 33 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 34 | enable_lapic(); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 35 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 36 | /* Do some early chipset init, necessary for RAM init to work */ |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 37 | i82801gx_early_init(); |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 38 | pineview_early_init(); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 39 | |
| 40 | post_code(0x30); |
| 41 | |
| 42 | s3resume = southbridge_detect_s3_resume(); |
| 43 | |
| 44 | if (s3resume) { |
| 45 | boot_path = BOOT_PATH_RESUME; |
| 46 | } else { |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame^] | 47 | if (mchbar_read32(PMSTS) & (1 << 8)) /* HOT RESET */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 48 | boot_path = BOOT_PATH_RESET; |
| 49 | else |
| 50 | boot_path = BOOT_PATH_NORMAL; |
| 51 | } |
| 52 | |
| 53 | get_mb_spd_addrmap(&spd_addrmap[0]); |
| 54 | |
| 55 | printk(BIOS_DEBUG, "Initializing memory\n"); |
| 56 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 57 | sdram_initialize(boot_path, spd_addrmap); |
| 58 | timestamp_add_now(TS_AFTER_INITRAM); |
| 59 | printk(BIOS_DEBUG, "Memory initialized\n"); |
| 60 | |
| 61 | post_code(0x31); |
| 62 | |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 63 | mb_pirq_setup(); |
| 64 | |
| 65 | rcba_config(); |
| 66 | |
| 67 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 68 | |
| 69 | if (!cbmem_was_initted && s3resume) { |
| 70 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | 363b771 | 2019-04-28 18:07:02 +0200 | [diff] [blame] | 71 | system_reset(); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | romstage_handoff_init(s3resume); |
| 75 | } |