Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 16 | #include <timestamp.h> |
| 17 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 19 | #include <cbmem.h> |
Elyes HAOUAS | 363b771 | 2019-04-28 18:07:02 +0200 | [diff] [blame] | 20 | #include <cf9_reset.h> |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 21 | #include <romstage_handoff.h> |
| 22 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Rudolph | 425e75a | 2019-03-24 15:06:17 +0100 | [diff] [blame] | 23 | #include <southbridge/intel/common/pmclib.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 24 | #include <arch/romstage.h> |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 25 | #include <cpu/x86/lapic.h> |
| 26 | #include "raminit.h" |
| 27 | #include "pineview.h" |
| 28 | |
| 29 | static void rcba_config(void) |
| 30 | { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame^] | 31 | /* Set up Virtual Channel 0 */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 32 | RCBA32(0x0014) = 0x80000001; |
| 33 | RCBA32(0x001c) = 0x03128010; |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 34 | } |
| 35 | |
| 36 | __weak void mb_pirq_setup(void) |
| 37 | { |
| 38 | } |
| 39 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame^] | 40 | /* The romstage entry point for this platform is not mainboard-specific, hence the name. */ |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 41 | void mainboard_romstage_entry(void) |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 42 | { |
| 43 | u8 spd_addrmap[4] = {}; |
| 44 | int boot_path, cbmem_was_initted; |
| 45 | int s3resume = 0; |
| 46 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 47 | enable_lapic(); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 48 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame^] | 49 | /* Do some early chipset init, necessary for RAM init to work */ |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 50 | i82801gx_early_init(); |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame^] | 51 | pineview_early_init(); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 52 | |
| 53 | post_code(0x30); |
| 54 | |
| 55 | s3resume = southbridge_detect_s3_resume(); |
| 56 | |
| 57 | if (s3resume) { |
| 58 | boot_path = BOOT_PATH_RESUME; |
| 59 | } else { |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame^] | 60 | if (MCHBAR32(PMSTS) & (1 << 8)) /* HOT RESET */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 61 | boot_path = BOOT_PATH_RESET; |
| 62 | else |
| 63 | boot_path = BOOT_PATH_NORMAL; |
| 64 | } |
| 65 | |
| 66 | get_mb_spd_addrmap(&spd_addrmap[0]); |
| 67 | |
| 68 | printk(BIOS_DEBUG, "Initializing memory\n"); |
| 69 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 70 | sdram_initialize(boot_path, spd_addrmap); |
| 71 | timestamp_add_now(TS_AFTER_INITRAM); |
| 72 | printk(BIOS_DEBUG, "Memory initialized\n"); |
| 73 | |
| 74 | post_code(0x31); |
| 75 | |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 76 | mb_pirq_setup(); |
| 77 | |
| 78 | rcba_config(); |
| 79 | |
| 80 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 81 | |
| 82 | if (!cbmem_was_initted && s3resume) { |
| 83 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | 363b771 | 2019-04-28 18:07:02 +0200 | [diff] [blame] | 84 | system_reset(); |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | romstage_handoff_init(s3resume); |
| 88 | } |