Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <amdblocks/apob_cache.h> |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame] | 4 | #include <amdblocks/ioapic.h> |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 5 | #include <amdblocks/memmap.h> |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 6 | #include <assert.h> |
Felix Held | e1f6db5 | 2022-11-22 17:18:21 +0100 | [diff] [blame] | 7 | #include <console/console.h> |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 8 | #include <console/uart.h> |
Felix Held | d0b5164 | 2021-04-08 22:25:19 +0200 | [diff] [blame] | 9 | #include <device/device.h> |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 10 | #include <fsp/api.h> |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 11 | #include <soc/platform_descriptors.h> |
Karthikeyan Ramasubramanian | cdbedb6 | 2021-05-10 17:02:58 -0600 | [diff] [blame] | 12 | #include <soc/pci_devs.h> |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 13 | #include <string.h> |
| 14 | #include <types.h> |
Felix Held | 2ec44ec | 2022-05-06 17:46:06 +0200 | [diff] [blame] | 15 | #include <vendorcode/amd/fsp/cezanne/FspUsb.h> |
Felix Held | d0b5164 | 2021-04-08 22:25:19 +0200 | [diff] [blame] | 16 | #include "chip.h" |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 17 | |
Martin Roth | 9d9dae1 | 2021-05-12 13:03:21 -0600 | [diff] [blame] | 18 | __weak void mb_pre_fspm(void) |
| 19 | { |
| 20 | } |
| 21 | |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 22 | static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg, |
| 23 | const fsp_dxio_descriptor *descs, size_t num) |
| 24 | { |
| 25 | size_t i; |
| 26 | |
| 27 | ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT, |
| 28 | "Too many DXIO descriptors provided."); |
| 29 | |
| 30 | for (i = 0; i < num; i++) { |
| 31 | memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0])); |
| 32 | } |
| 33 | } |
| 34 | |
| 35 | static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg, |
| 36 | const fsp_ddi_descriptor *descs, size_t num) |
| 37 | { |
| 38 | size_t i; |
| 39 | |
| 40 | ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT, |
| 41 | "Too many DDI descriptors provided."); |
| 42 | |
| 43 | for (i = 0; i < num; i++) { |
| 44 | memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0])); |
| 45 | } |
| 46 | } |
| 47 | |
| 48 | static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) |
| 49 | { |
Jon Murphy | fcccff3 | 2022-03-16 11:03:38 -0600 | [diff] [blame] | 50 | const fsp_dxio_descriptor *fsp_dxio = NULL; |
| 51 | const fsp_ddi_descriptor *fsp_ddi = NULL; |
| 52 | size_t num_dxio = 0; |
| 53 | size_t num_ddi = 0; |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 54 | |
| 55 | mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, |
| 56 | &fsp_ddi, &num_ddi); |
| 57 | fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio); |
| 58 | fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi); |
| 59 | } |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 60 | |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame] | 61 | static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg) |
| 62 | { |
| 63 | mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR; |
| 64 | mcfg->gnb_ioapic_id = GNB_IOAPIC_ID; |
| 65 | mcfg->fch_ioapic_id = FCH_IOAPIC_ID; |
| 66 | } |
| 67 | |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 68 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 69 | { |
| 70 | FSP_M_CONFIG *mcfg = &mupd->FspmConfig; |
Felix Held | d0b5164 | 2021-04-08 22:25:19 +0200 | [diff] [blame] | 71 | const struct soc_amd_cezanne_config *config = config_of_soc(); |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 72 | |
| 73 | mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); |
| 74 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 75 | mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS; |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 76 | mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 77 | mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); |
| 78 | mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 79 | mcfg->serial_port_baudrate = get_uart_baudrate(); |
| 80 | mcfg->serial_port_refclk = uart_platform_refclk(); |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 81 | |
Felix Held | d0b5164 | 2021-04-08 22:25:19 +0200 | [diff] [blame] | 82 | /* 0 is default */ |
| 83 | mcfg->ccx_down_core_mode = config->downcore_mode; |
| 84 | mcfg->ccx_disable_smt = config->disable_smt; |
| 85 | |
Felix Held | d3be9ba | 2021-04-19 21:40:35 +0200 | [diff] [blame] | 86 | /* when stt_control isn't 1, FSP will ignore the other stt values */ |
| 87 | mcfg->stt_control = config->stt_control; |
| 88 | mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count; |
| 89 | mcfg->stt_min_limit = config->stt_min_limit; |
| 90 | mcfg->stt_m1 = config->stt_m1; |
| 91 | mcfg->stt_m2 = config->stt_m2; |
| 92 | mcfg->stt_m3 = config->stt_m3; |
| 93 | mcfg->stt_m4 = config->stt_m4; |
| 94 | mcfg->stt_m5 = config->stt_m5; |
| 95 | mcfg->stt_m6 = config->stt_m6; |
| 96 | mcfg->stt_c_apu = config->stt_c_apu; |
| 97 | mcfg->stt_c_gpu = config->stt_c_gpu; |
| 98 | mcfg->stt_c_hs2 = config->stt_c_hs2; |
| 99 | mcfg->stt_alpha_apu = config->stt_alpha_apu; |
| 100 | mcfg->stt_alpha_gpu = config->stt_alpha_gpu; |
| 101 | mcfg->stt_alpha_hs2 = config->stt_alpha_hs2; |
| 102 | mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu; |
| 103 | mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu; |
| 104 | mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2; |
| 105 | mcfg->stt_error_coeff = config->stt_error_coeff; |
| 106 | mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient; |
| 107 | |
| 108 | /* all following fields being 0 is a valid config */ |
| 109 | mcfg->stapm_boost = config->stapm_boost; |
Martin Roth | 9c17665 | 2021-04-23 12:24:35 -0600 | [diff] [blame] | 110 | mcfg->stapm_time_constant = config->stapm_time_constant_s; |
Felix Held | d3be9ba | 2021-04-19 21:40:35 +0200 | [diff] [blame] | 111 | mcfg->apu_only_sppt_limit = config->apu_only_sppt_limit; |
Martin Roth | 9c17665 | 2021-04-23 12:24:35 -0600 | [diff] [blame] | 112 | mcfg->sustained_power_limit = config->sustained_power_limit_mW; |
| 113 | mcfg->fast_ppt_limit = config->fast_ppt_limit_mW; |
| 114 | mcfg->slow_ppt_limit = config->slow_ppt_limit_mW; |
Martin Roth | 029d997 | 2021-04-23 12:22:59 -0600 | [diff] [blame] | 115 | mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant_s; |
| 116 | mcfg->thermctl_limit = config->thermctl_limit_degreeC; |
Felix Held | d3be9ba | 2021-04-19 21:40:35 +0200 | [diff] [blame] | 117 | |
| 118 | /* 0 is default */ |
| 119 | mcfg->smartshift_enable = config->smartshift_enable; |
| 120 | |
| 121 | /* 0 is default */ |
| 122 | mcfg->system_configuration = config->system_configuration; |
| 123 | |
| 124 | /* when cppc_ctrl is 0 the other values won't be used */ |
| 125 | mcfg->cppc_ctrl = config->cppc_ctrl; |
| 126 | mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range; |
| 127 | mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range; |
| 128 | mcfg->cppc_epp_max_range = config->cppc_epp_max_range; |
| 129 | mcfg->cppc_epp_min_range = config->cppc_epp_min_range; |
| 130 | mcfg->cppc_preferred_cores = config->cppc_preferred_cores; |
| 131 | |
Karthikeyan Ramasubramanian | 5ad85d9 | 2021-04-22 16:59:08 -0600 | [diff] [blame] | 132 | /* S0i3 enable */ |
| 133 | mcfg->s0i3_enable = config->s0ix_enable; |
Jason Glenesk | 0834d86 | 2021-08-03 03:39:36 -0700 | [diff] [blame] | 134 | mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN); |
Karthikeyan Ramasubramanian | 5ad85d9 | 2021-04-22 16:59:08 -0600 | [diff] [blame] | 135 | |
Chris Wang | 0679392 | 2021-04-29 00:11:01 +0800 | [diff] [blame] | 136 | /* voltage regulator telemetry settings */ |
| 137 | mcfg->telemetry_vddcrvddfull_scale_current = |
| 138 | config->telemetry_vddcrvddfull_scale_current_mA; |
| 139 | mcfg->telemetry_vddcrvddoffset = |
| 140 | config->telemetry_vddcrvddoffset; |
| 141 | mcfg->telemetry_vddcrsocfull_scale_current = |
| 142 | config->telemetry_vddcrsocfull_scale_current_mA; |
| 143 | mcfg->telemetry_vddcrsocOffset = |
| 144 | config->telemetry_vddcrsocoffset; |
| 145 | |
Felix Held | 9a24c3f | 2021-05-25 20:45:08 +0200 | [diff] [blame] | 146 | /* PCIe power vs. speed */ |
| 147 | mcfg->pspp_policy = config->pspp_policy; |
| 148 | |
Felix Held | a0b2510 | 2021-09-20 15:09:05 +0200 | [diff] [blame] | 149 | mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda)); |
| 150 | mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda)); |
| 151 | mcfg->sata_enable = is_dev_enabled(DEV_PTR(sata_0)) || is_dev_enabled(DEV_PTR(sata_1)); |
Karthikeyan Ramasubramanian | cdbedb6 | 2021-05-10 17:02:58 -0600 | [diff] [blame] | 152 | |
Julian Schroeder | 4671983 | 2021-09-07 14:54:19 -0500 | [diff] [blame] | 153 | if (config->usb_phy_custom) { |
Fred Reitberger | 727bebb | 2022-05-06 15:59:15 -0400 | [diff] [blame] | 154 | /* devicetree config is const, use local copy */ |
| 155 | static struct usb_phy_config lcl_usb_phy; |
| 156 | lcl_usb_phy = config->usb_phy; |
Felix Held | 75873db | 2022-11-22 17:05:05 +0100 | [diff] [blame] | 157 | lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; |
| 158 | lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; |
| 159 | lcl_usb_phy.TableLength = sizeof(struct usb_phy_config); |
Felix Held | e1f6db5 | 2022-11-22 17:18:21 +0100 | [diff] [blame] | 160 | if ((uintptr_t)&lcl_usb_phy <= UINT32_MAX) { |
| 161 | mcfg->usb_phy_ptr = (uint32_t)(uintptr_t)&lcl_usb_phy; |
| 162 | } else { |
| 163 | printk(BIOS_ERR, "USB PHY config struct above 4GB; can't pass USB PHY " |
| 164 | "configuration to 32 bit FSP.\n"); |
| 165 | mcfg->usb_phy_ptr = 0; |
| 166 | } |
Felix Held | 575f1ec | 2021-11-10 00:15:16 +0100 | [diff] [blame] | 167 | } else { |
Felix Held | e1f6db5 | 2022-11-22 17:18:21 +0100 | [diff] [blame] | 168 | mcfg->usb_phy_ptr = 0; |
Felix Held | 575f1ec | 2021-11-10 00:15:16 +0100 | [diff] [blame] | 169 | } |
Julian Schroeder | d2f3308 | 2021-05-11 10:44:13 -0500 | [diff] [blame] | 170 | |
Zheng Bao | 8b54c0e | 2021-12-06 23:09:37 +0800 | [diff] [blame] | 171 | if (config->edp_phy_override) { |
| 172 | mcfg->edp_phy_override = config->edp_phy_override; |
| 173 | mcfg->edp_physel = config->edp_physel; |
| 174 | mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level; |
| 175 | mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main; |
| 176 | mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre; |
| 177 | mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post; |
| 178 | mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl; |
| 179 | } |
| 180 | |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 181 | fsp_fill_pcie_ddi_descriptors(mcfg); |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame] | 182 | fsp_assign_ioapic_upds(mcfg); |
Martin Roth | 9d9dae1 | 2021-05-12 13:03:21 -0600 | [diff] [blame] | 183 | mb_pre_fspm(); |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 184 | } |