blob: baf4ca8b853e2af69aadffa6f02743614a5bbde3 [file] [log] [blame]
Felix Held2421de62021-03-26 01:13:53 +01001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <amdblocks/apob_cache.h>
4#include <amdblocks/memmap.h>
Matt Papageorgeea0f2252021-03-30 11:41:22 -05005#include <assert.h>
Felix Held2421de62021-03-26 01:13:53 +01006#include <console/uart.h>
Felix Heldd0b51642021-04-08 22:25:19 +02007#include <device/device.h>
Felix Held2421de62021-03-26 01:13:53 +01008#include <fsp/api.h>
Matt Papageorgeea0f2252021-03-30 11:41:22 -05009#include <soc/platform_descriptors.h>
10#include <string.h>
11#include <types.h>
Felix Heldd0b51642021-04-08 22:25:19 +020012#include "chip.h"
Matt Papageorgeea0f2252021-03-30 11:41:22 -050013
14static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg,
15 const fsp_dxio_descriptor *descs, size_t num)
16{
17 size_t i;
18
19 ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT,
20 "Too many DXIO descriptors provided.");
21
22 for (i = 0; i < num; i++) {
23 memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0]));
24 }
25}
26
27static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg,
28 const fsp_ddi_descriptor *descs, size_t num)
29{
30 size_t i;
31
32 ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT,
33 "Too many DDI descriptors provided.");
34
35 for (i = 0; i < num; i++) {
36 memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0]));
37 }
38}
39
40static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg)
41{
42 const fsp_dxio_descriptor *fsp_dxio;
43 const fsp_ddi_descriptor *fsp_ddi;
44 size_t num_dxio;
45 size_t num_ddi;
46
47 mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio,
48 &fsp_ddi, &num_ddi);
49 fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio);
50 fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi);
51}
Felix Held2421de62021-03-26 01:13:53 +010052
53void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
54{
55 FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
Felix Heldd0b51642021-04-08 22:25:19 +020056 const struct soc_amd_cezanne_config *config = config_of_soc();
Felix Held2421de62021-03-26 01:13:53 +010057
58 mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
59
60 mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
61 mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
62 mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
63 mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
64 mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
Felix Held2421de62021-03-26 01:13:53 +010065 mcfg->serial_port_baudrate = get_uart_baudrate();
66 mcfg->serial_port_refclk = uart_platform_refclk();
Matt Papageorgeea0f2252021-03-30 11:41:22 -050067
Felix Heldd0b51642021-04-08 22:25:19 +020068 /* 0 is default */
69 mcfg->ccx_down_core_mode = config->downcore_mode;
70 mcfg->ccx_disable_smt = config->disable_smt;
71
Matt Papageorgeea0f2252021-03-30 11:41:22 -050072 fsp_fill_pcie_ddi_descriptors(mcfg);
Felix Held2421de62021-03-26 01:13:53 +010073}