Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 3 | #include <console/console.h> |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 4 | #include <device/mmio.h> |
| 5 | #include <device/device.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 7 | #include <device/pci_def.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 8 | #include <option.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 9 | #include <types.h> |
| 10 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 11 | #include "sandybridge.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 12 | |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 13 | static void systemagent_vtd_init(void) |
| 14 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 15 | const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 16 | if (capid0_a & (1 << 23)) |
| 17 | return; |
| 18 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 19 | /* Setup BARs */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 20 | mchbar_write32(GFXVTBAR + 4, GFXVT_BASE >> 32); |
| 21 | mchbar_write32(GFXVTBAR + 0, GFXVT_BASE | 1); |
| 22 | mchbar_write32(VTVC0BAR + 4, VTVC0_BASE >> 32); |
| 23 | mchbar_write32(VTVC0BAR + 0, VTVC0_BASE | 1); |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 24 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 25 | /* Lock policies */ |
Elyes Haouas | ee4646e | 2022-12-04 09:16:07 +0100 | [diff] [blame] | 26 | write32p(GFXVT_BASE + 0xff0, 0x80000000); |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 27 | |
| 28 | const struct device *const azalia = pcidev_on_root(0x1b, 0); |
| 29 | if (azalia && azalia->enabled) { |
Elyes Haouas | ee4646e | 2022-12-04 09:16:07 +0100 | [diff] [blame] | 30 | write32p(VTVC0_BASE + 0xff0, 0x20000000); |
| 31 | write32p(VTVC0_BASE + 0xff0, 0xa0000000); |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 32 | } else { |
Elyes Haouas | ee4646e | 2022-12-04 09:16:07 +0100 | [diff] [blame] | 33 | write32p(VTVC0_BASE + 0xff0, 0x80000000); |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 34 | } |
| 35 | } |
| 36 | |
| 37 | static void enable_pam_region(void) |
| 38 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 39 | pci_write_config8(HOST_BRIDGE, PAM0, 0x30); |
| 40 | pci_write_config8(HOST_BRIDGE, PAM1, 0x33); |
| 41 | pci_write_config8(HOST_BRIDGE, PAM2, 0x33); |
| 42 | pci_write_config8(HOST_BRIDGE, PAM3, 0x33); |
| 43 | pci_write_config8(HOST_BRIDGE, PAM4, 0x33); |
| 44 | pci_write_config8(HOST_BRIDGE, PAM5, 0x33); |
| 45 | pci_write_config8(HOST_BRIDGE, PAM6, 0x33); |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 46 | } |
| 47 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 48 | static void sandybridge_setup_bars(void) |
| 49 | { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 50 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 51 | /* Set up all hardcoded northbridge BARs */ |
Angel Pons | d9e58dc | 2021-01-20 01:22:20 +0100 | [diff] [blame] | 52 | pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); |
| 53 | pci_write_config32(HOST_BRIDGE, EPBAR + 4, 0); |
| 54 | pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); |
| 55 | pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0); |
| 56 | pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); |
| 57 | pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 58 | |
Patrick Rudolph | 9005071 | 2019-03-25 09:53:23 +0100 | [diff] [blame] | 59 | printk(BIOS_DEBUG, " done\n"); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 60 | } |
| 61 | |
| 62 | static void sandybridge_setup_graphics(void) |
| 63 | { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 64 | u16 reg16; |
Angel Pons | 9733f6a | 2020-06-07 19:23:03 +0200 | [diff] [blame] | 65 | u8 gfxsize; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 66 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 67 | reg16 = pci_read_config16(PCI_DEV(0, 2, 0), PCI_DEVICE_ID); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 68 | switch (reg16) { |
| 69 | case 0x0102: /* GT1 Desktop */ |
| 70 | case 0x0106: /* GT1 Mobile */ |
| 71 | case 0x010a: /* GT1 Server */ |
| 72 | case 0x0112: /* GT2 Desktop */ |
| 73 | case 0x0116: /* GT2 Mobile */ |
| 74 | case 0x0122: /* GT2 Desktop >=1.3GHz */ |
| 75 | case 0x0126: /* GT2 Mobile >=1.3GHz */ |
Patrick Rudolph | 03a88d3 | 2015-07-05 13:29:41 +0200 | [diff] [blame] | 76 | case 0x0152: /* IvyBridge */ |
Stefan Reinauer | 816e9d1 | 2013-01-14 10:25:43 -0800 | [diff] [blame] | 77 | case 0x0156: /* IvyBridge */ |
Damien Zammit | a10bde9 | 2014-10-23 13:29:32 +1100 | [diff] [blame] | 78 | case 0x0162: /* IvyBridge */ |
Stefan Reinauer | 816e9d1 | 2013-01-14 10:25:43 -0800 | [diff] [blame] | 79 | case 0x0166: /* IvyBridge */ |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 80 | case 0x016a: /* IvyBridge */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 81 | break; |
| 82 | default: |
| 83 | printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n"); |
| 84 | return; |
| 85 | } |
| 86 | |
| 87 | printk(BIOS_DEBUG, "Initializing Graphics...\n"); |
| 88 | |
Angel Pons | f9c9390 | 2020-11-02 22:21:54 +0100 | [diff] [blame] | 89 | /* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */ |
Angel Pons | 88dcb31 | 2021-04-26 17:10:28 +0200 | [diff] [blame] | 90 | gfxsize = get_uint_option("gfx_uma_size", 0); |
Angel Pons | f9c9390 | 2020-11-02 22:21:54 +0100 | [diff] [blame] | 91 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 92 | reg16 = pci_read_config16(HOST_BRIDGE, GGC); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 93 | reg16 &= ~0x00f8; |
Vladimir Serbinenko | 5fc04d1 | 2014-08-03 01:59:38 +0200 | [diff] [blame] | 94 | reg16 |= (gfxsize + 1) << 3; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 95 | /* Program GTT memory by setting GGC[9:8] = 2MB */ |
| 96 | reg16 &= ~0x0300; |
| 97 | reg16 |= 2 << 8; |
| 98 | /* Enable VGA decode */ |
| 99 | reg16 &= ~0x0002; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 100 | pci_write_config16(HOST_BRIDGE, GGC, reg16); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 101 | |
| 102 | /* Enable 256MB aperture */ |
Angel Pons | 9733f6a | 2020-06-07 19:23:03 +0200 | [diff] [blame] | 103 | pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 104 | |
| 105 | /* Erratum workarounds */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 106 | mchbar_setbits32(SAPMCTL, 1 << 9 | 1 << 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 107 | |
| 108 | /* Enable SA Clock Gating */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 109 | mchbar_setbits32(SAPMCTL, 1 << 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 110 | |
| 111 | /* GPU RC6 workaround for sighting 366252 */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 112 | mchbar_setbits32(SSKPD_HI, 1 << 31); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 113 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 114 | /* VLW (Virtual Legacy Wire?) */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 115 | mchbar_clrbits32(0x6120, 1 << 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 116 | |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 117 | mchbar_setbits32(INTRDIRCTL, 1 << 4 | 1 << 5); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 118 | } |
| 119 | |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 120 | static void start_peg_link_training(void) |
| 121 | { |
Angel Pons | 9733f6a | 2020-06-07 19:23:03 +0200 | [diff] [blame] | 122 | u32 deven; |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 123 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 124 | const u16 base_rev = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID) & BASE_REV_MASK; |
| 125 | /* |
| 126 | * PEG on IvyBridge+ needs a special startup sequence. |
| 127 | * As the MRC has its own initialization code skip it. |
| 128 | */ |
| 129 | if ((base_rev != BASE_REV_IVB) || CONFIG(HAVE_MRC)) |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 130 | return; |
| 131 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 132 | deven = pci_read_config32(HOST_BRIDGE, DEVEN); |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 133 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 134 | /* |
| 135 | * For each PEG device, set bit 5 to use three retries for OC (Offset Calibration). |
| 136 | * We also clear DEFER_OC (bit 16) in order to start PEG training. |
| 137 | */ |
Angel Pons | 9733f6a | 2020-06-07 19:23:03 +0200 | [diff] [blame] | 138 | if (deven & DEVEN_PEG10) |
| 139 | pci_update_config32(PCI_DEV(0, 1, 0), AFE_PWRON, ~(1 << 16), 1 << 5); |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 140 | |
Angel Pons | 9733f6a | 2020-06-07 19:23:03 +0200 | [diff] [blame] | 141 | if (deven & DEVEN_PEG11) |
| 142 | pci_update_config32(PCI_DEV(0, 1, 1), AFE_PWRON, ~(1 << 16), 1 << 5); |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 143 | |
Angel Pons | 9733f6a | 2020-06-07 19:23:03 +0200 | [diff] [blame] | 144 | if (deven & DEVEN_PEG12) |
| 145 | pci_update_config32(PCI_DEV(0, 1, 2), AFE_PWRON, ~(1 << 16), 1 << 5); |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 146 | |
Angel Pons | 9733f6a | 2020-06-07 19:23:03 +0200 | [diff] [blame] | 147 | if (deven & DEVEN_PEG60) |
| 148 | pci_update_config32(PCI_DEV(0, 6, 0), AFE_PWRON, ~(1 << 16), 1 << 5); |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 149 | } |
| 150 | |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 151 | void systemagent_early_init(void) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 152 | { |
| 153 | u32 capid0_a; |
| 154 | u8 reg8; |
| 155 | |
| 156 | /* Device ID Override Enable should be done very early */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 157 | capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 158 | if (capid0_a & (1 << 10)) { |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 159 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
| 160 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 161 | reg8 = pci_read_config8(HOST_BRIDGE, DIDOR); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 162 | reg8 &= ~7; /* Clear 2:0 */ |
| 163 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 164 | if (is_mobile) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 165 | reg8 |= 1; /* Set bit 0 */ |
| 166 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 167 | pci_write_config8(HOST_BRIDGE, DIDOR, reg8); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | /* Setup all BARs required for early PCIe and raminit */ |
| 171 | sandybridge_setup_bars(); |
| 172 | |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 173 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 174 | enable_pam_region(); |
| 175 | |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 176 | /* Setup IOMMU BARs */ |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 177 | systemagent_vtd_init(); |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 178 | |
Patrick Rudolph | 2a510a7 | 2015-07-28 07:51:10 +0200 | [diff] [blame] | 179 | /* Device Enable, don't touch PEG bits */ |
Angel Pons | 9733f6a | 2020-06-07 19:23:03 +0200 | [diff] [blame] | 180 | pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_IGD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 181 | |
| 182 | sandybridge_setup_graphics(); |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 183 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 184 | /* |
| 185 | * Write magic values to start PEG link training. This should be done in PCI device |
| 186 | * enumeration, but the PCIe specification requires to wait at least 100msec after |
| 187 | * reset for devices to come up. As we don't want to increase boot time, enable it |
| 188 | * early and assume that PEG is up as soon as PCI enumeration starts. |
| 189 | * |
| 190 | * TODO: use timestamps to ensure the timings are met. |
| 191 | */ |
Patrick Rudolph | e4f9d5c | 2015-10-15 11:09:15 +0200 | [diff] [blame] | 192 | start_peg_link_training(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 193 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 194 | |
Kyösti Mälkki | 4ce0a07 | 2021-02-17 18:10:49 +0200 | [diff] [blame] | 195 | void northbridge_romstage_finalize(void) |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 196 | { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 197 | mchbar_write16(SSKPD_HI, 0xcafe); |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 198 | } |