nb/intel/sandybridge: Tidy up code and comments
- Reformat some lines of code
- Move MCHBAR registers and documentation into a separate file
- Add a few missing macros
- Rename some registers
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
With BUILD_TIMELESS=1, this commit does not change the result of:
- Asus P8Z77-V LX2 with native raminit.
- Asus P8Z77-M PRO with MRC raminit.
Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 10ac071..390fadc 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -25,49 +25,49 @@
static void systemagent_vtd_init(void)
{
- const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);
+ const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
if (capid0_a & (1 << 23))
return;
- /* setup BARs */
- MCHBAR32(VTD1_BASE + 4) = IOMMU_BASE1 >> 32;
- MCHBAR32(VTD1_BASE) = IOMMU_BASE1 | 1;
- MCHBAR32(VTD2_BASE + 4) = IOMMU_BASE2 >> 32;
- MCHBAR32(VTD2_BASE) = IOMMU_BASE2 | 1;
+ /* Setup BARs */
+ MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE >> 32;
+ MCHBAR32(GFXVTBAR) = GFXVT_BASE | 1;
+ MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE >> 32;
+ MCHBAR32(VTVC0BAR) = VTVC0_BASE | 1;
- /* lock policies */
- write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000);
+ /* Lock policies */
+ write32((void *)(GFXVT_BASE + 0xff0), 0x80000000);
const struct device *const azalia = pcidev_on_root(0x1b, 0);
if (azalia && azalia->enabled) {
- write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000);
- write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000);
+ write32((void *)(VTVC0_BASE + 0xff0), 0x20000000);
+ write32((void *)(VTVC0_BASE + 0xff0), 0xa0000000);
} else {
- write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000);
+ write32((void *)(VTVC0_BASE + 0xff0), 0x80000000);
}
}
static void enable_pam_region(void)
{
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
- pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
+ pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
}
static void sandybridge_setup_bars(void)
{
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
- pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1);
+ pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
+ pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32);
+ pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32);
printk(BIOS_DEBUG, " done\n");
}
@@ -76,10 +76,9 @@
{
u32 reg32;
u16 reg16;
- u8 reg8;
- u8 gfxsize;
+ u8 reg8, gfxsize;
- reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID);
+ reg16 = pci_read_config16(PCI_DEV(0, 2, 0), PCI_DEVICE_ID);
switch (reg16) {
case 0x0102: /* GT1 Desktop */
case 0x0106: /* GT1 Mobile */
@@ -105,7 +104,7 @@
/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
gfxsize = 0;
}
- reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC);
+ reg16 = pci_read_config16(HOST_BRIDGE, GGC);
reg16 &= ~0x00f8;
reg16 |= (gfxsize + 1) << 3;
/* Program GTT memory by setting GGC[9:8] = 2MB */
@@ -113,7 +112,7 @@
reg16 |= 2 << 8;
/* Enable VGA decode */
reg16 &= ~0x0002;
- pci_write_config16(PCI_DEV(0,0,0), GGC, reg16);
+ pci_write_config16(HOST_BRIDGE, GGC, reg16);
/* Enable 256MB aperture */
reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC);
@@ -123,7 +122,7 @@
/* Erratum workarounds */
reg32 = MCHBAR32(SAPMCTL);
- reg32 |= (1 << 9)|(1 << 10);
+ reg32 |= (1 << 9) | (1 << 10);
MCHBAR32(SAPMCTL) = reg32;
/* Enable SA Clock Gating */
@@ -131,52 +130,56 @@
MCHBAR32(SAPMCTL) = reg32 | 1;
/* GPU RC6 workaround for sighting 366252 */
- reg32 = MCHBAR32(0x5d14);
+ reg32 = MCHBAR32(SSKPD_HI);
reg32 |= (1 << 31);
- MCHBAR32(0x5d14) = reg32;
+ MCHBAR32(SSKPD_HI) = reg32;
- /* VLW */
+ /* VLW (Virtual Legacy Wire?) */
reg32 = MCHBAR32(0x6120);
reg32 &= ~(1 << 0);
MCHBAR32(0x6120) = reg32;
- reg32 = MCHBAR32(PAIR_CTL);
+ reg32 = MCHBAR32(INTRDIRCTL);
reg32 |= (1 << 4) | (1 << 5);
- MCHBAR32(PAIR_CTL) = reg32;
+ MCHBAR32(INTRDIRCTL) = reg32;
}
static void start_peg_link_training(void)
{
- u32 tmp;
- u32 deven;
+ u32 tmp, deven;
- /* PEG on IvyBridge+ needs a special startup sequence.
- * As the MRC has its own initialization code skip it. */
- if (((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) &
- BASE_REV_MASK) != BASE_REV_IVB) ||
- CONFIG(HAVE_MRC))
+ const u16 base_rev = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID) & BASE_REV_MASK;
+ /*
+ * PEG on IvyBridge+ needs a special startup sequence.
+ * As the MRC has its own initialization code skip it.
+ */
+ if ((base_rev != BASE_REV_IVB) || CONFIG(HAVE_MRC))
return;
- deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+ deven = pci_read_config32(HOST_BRIDGE, DEVEN);
+ /*
+ * For each PEG device, set bit 5 to use three retries for OC (Offset Calibration).
+ * We also clear DEFER_OC (bit 16) in order to start PEG training.
+ */
if (deven & DEVEN_PEG10) {
- tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16);
- pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5));
+ tmp = pci_read_config32(PCI_DEV(0, 1, 0), AFE_PWRON) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 0), AFE_PWRON, tmp | (1 << 5));
}
if (deven & DEVEN_PEG11) {
- tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16);
- pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5));
+ tmp = pci_read_config32(PCI_DEV(0, 1, 1), AFE_PWRON) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 1), AFE_PWRON, tmp | (1 << 5));
}
if (deven & DEVEN_PEG12) {
- tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16);
- pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5));
+ tmp = pci_read_config32(PCI_DEV(0, 1, 2), AFE_PWRON) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 2), AFE_PWRON, tmp | (1 << 5));
}
if (deven & DEVEN_PEG60) {
- tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16);
- pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5));
+ tmp = pci_read_config32(PCI_DEV(0, 6, 0), AFE_PWRON) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 6, 0), AFE_PWRON, tmp | (1 << 5));
}
}
@@ -187,17 +190,17 @@
u8 reg8;
/* Device ID Override Enable should be done very early */
- capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
+ capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
if (capid0_a & (1 << 10)) {
const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE;
- reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
+ reg8 = pci_read_config8(HOST_BRIDGE, DIDOR);
reg8 &= ~7; /* Clear 2:0 */
if (is_mobile)
reg8 |= 1; /* Set bit 0 */
- pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
+ pci_write_config8(HOST_BRIDGE, DIDOR, reg8);
}
/* Setup all BARs required for early PCIe and raminit */
@@ -210,24 +213,25 @@
systemagent_vtd_init();
/* Device Enable, don't touch PEG bits */
- deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD;
- pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven);
+ deven = pci_read_config32(HOST_BRIDGE, DEVEN) | DEVEN_IGD;
+ pci_write_config32(HOST_BRIDGE, DEVEN, deven);
sandybridge_setup_graphics();
- /* Write magic value to start PEG link training.
- * This should be done in PCI device enumeration, but
- * the PCIe specification requires to wait at least 100msec
- * after reset for devices to come up.
- * As we don't want to increase boot time, enable it early and
- * assume the PEG is up as soon as PCI enumeration starts.
- * TODO: use time stamps to ensure the timings are met */
+ /*
+ * Write magic values to start PEG link training. This should be done in PCI device
+ * enumeration, but the PCIe specification requires to wait at least 100msec after
+ * reset for devices to come up. As we don't want to increase boot time, enable it
+ * early and assume that PEG is up as soon as PCI enumeration starts.
+ *
+ * TODO: use timestamps to ensure the timings are met.
+ */
start_peg_link_training();
}
void northbridge_romstage_finalize(int s3resume)
{
- MCHBAR16(SSKPD) = 0xCAFE;
+ MCHBAR16(SSKPD_HI) = 0xCAFE;
romstage_handoff_init(s3resume);
}