nb/intel/sandybridge: Use new fixed BAR accessors
One instance in northbridge.c breaks reproduciblity when changed.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: I2148183827bcacc9e6edb91b26ad35eb2dae5090
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51866
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index b7ee322..922c4b7 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -17,10 +17,10 @@
return;
/* Setup BARs */
- MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE >> 32;
- MCHBAR32(GFXVTBAR) = GFXVT_BASE | 1;
- MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE >> 32;
- MCHBAR32(VTVC0BAR) = VTVC0_BASE | 1;
+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE >> 32);
+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE | 1);
+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE >> 32);
+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE | 1);
/* Lock policies */
write32((void *)(GFXVT_BASE + 0xff0), 0x80000000);
@@ -104,18 +104,18 @@
pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
/* Erratum workarounds */
- MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10));
+ mchbar_setbits32(SAPMCTL, 1 << 9 | 1 << 10);
/* Enable SA Clock Gating */
- MCHBAR32_OR(SAPMCTL, 1);
+ mchbar_setbits32(SAPMCTL, 1 << 0);
/* GPU RC6 workaround for sighting 366252 */
- MCHBAR32_OR(SSKPD_HI, 1 << 31);
+ mchbar_setbits32(SSKPD_HI, 1 << 31);
/* VLW (Virtual Legacy Wire?) */
- MCHBAR32_AND(0x6120, ~(1 << 0));
+ mchbar_clrbits32(0x6120, 1 << 0);
- MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5));
+ mchbar_setbits32(INTRDIRCTL, 1 << 4 | 1 << 5);
}
static void start_peg_link_training(void)
@@ -195,5 +195,5 @@
void northbridge_romstage_finalize(void)
{
- MCHBAR16(SSKPD_HI) = 0xCAFE;
+ mchbar_write16(SSKPD_HI, 0xcafe);
}