nb/intel/sandybridge: Use write32p()
Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 7acc5af..e3525135 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -23,14 +23,14 @@
mchbar_write32(VTVC0BAR + 0, VTVC0_BASE | 1);
/* Lock policies */
- write32((void *)(GFXVT_BASE + 0xff0), 0x80000000);
+ write32p(GFXVT_BASE + 0xff0, 0x80000000);
const struct device *const azalia = pcidev_on_root(0x1b, 0);
if (azalia && azalia->enabled) {
- write32((void *)(VTVC0_BASE + 0xff0), 0x20000000);
- write32((void *)(VTVC0_BASE + 0xff0), 0xa0000000);
+ write32p(VTVC0_BASE + 0xff0, 0x20000000);
+ write32p(VTVC0_BASE + 0xff0, 0xa0000000);
} else {
- write32((void *)(VTVC0_BASE + 0xff0), 0x80000000);
+ write32p(VTVC0_BASE + 0xff0, 0x80000000);
}
}