Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Nico Huber | c2e4642 | 2020-03-23 01:22:49 +0100 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 7 | #include <console/console.h> |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 8 | #include <bootmode.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include <delay.h> |
| 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 13 | #include <drivers/intel/gma/i915_reg.h> |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 14 | #include <drivers/intel/gma/i915.h> |
Nico Huber | 1822816 | 2017-06-08 16:31:57 +0200 | [diff] [blame] | 15 | #include <drivers/intel/gma/libgfxinit.h> |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 16 | #include <cpu/intel/haswell/haswell.h> |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 17 | #include <drivers/intel/gma/opregion.h> |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 18 | #include <string.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 19 | #include <types.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | |
| 21 | #include "chip.h" |
| 22 | #include "haswell.h" |
| 23 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 24 | struct gt_reg { |
| 25 | u32 reg; |
| 26 | u32 andmask; |
| 27 | u32 ormask; |
| 28 | }; |
| 29 | |
| 30 | static const struct gt_reg haswell_gt_setup[] = { |
| 31 | /* Enable Counters */ |
| 32 | { 0x0a248, 0x00000000, 0x00000016 }, |
| 33 | { 0x0a000, 0x00000000, 0x00070020 }, |
| 34 | { 0x0a180, 0xff3fffff, 0x15000000 }, |
| 35 | /* Enable DOP Clock Gating */ |
| 36 | { 0x09424, 0x00000000, 0x000003fd }, |
| 37 | /* Enable Unit Level Clock Gating */ |
| 38 | { 0x09400, 0x00000000, 0x00000080 }, |
| 39 | { 0x09404, 0x00000000, 0x40401000 }, |
| 40 | { 0x09408, 0x00000000, 0x00000000 }, |
| 41 | { 0x0940c, 0x00000000, 0x02000001 }, |
| 42 | { 0x0a008, 0x00000000, 0x08000000 }, |
| 43 | /* Wake Rate Limits */ |
| 44 | { 0x0a090, 0xffffffff, 0x00000000 }, |
| 45 | { 0x0a098, 0xffffffff, 0x03e80000 }, |
| 46 | { 0x0a09c, 0xffffffff, 0x00280000 }, |
| 47 | { 0x0a0a8, 0xffffffff, 0x0001e848 }, |
| 48 | { 0x0a0ac, 0xffffffff, 0x00000019 }, |
| 49 | /* Render/Video/Blitter Idle Max Count */ |
| 50 | { 0x02054, 0x00000000, 0x0000000a }, |
| 51 | { 0x12054, 0x00000000, 0x0000000a }, |
| 52 | { 0x22054, 0x00000000, 0x0000000a }, |
| 53 | /* RC Sleep / RCx Thresholds */ |
| 54 | { 0x0a0b0, 0xffffffff, 0x00000000 }, |
| 55 | { 0x0a0b4, 0xffffffff, 0x000003e8 }, |
| 56 | { 0x0a0b8, 0xffffffff, 0x0000c350 }, |
| 57 | /* RP Settings */ |
| 58 | { 0x0a010, 0xffffffff, 0x000f4240 }, |
| 59 | { 0x0a014, 0xffffffff, 0x12060000 }, |
| 60 | { 0x0a02c, 0xffffffff, 0x0000e808 }, |
| 61 | { 0x0a030, 0xffffffff, 0x0003bd08 }, |
| 62 | { 0x0a068, 0xffffffff, 0x000101d0 }, |
| 63 | { 0x0a06c, 0xffffffff, 0x00055730 }, |
| 64 | { 0x0a070, 0xffffffff, 0x0000000a }, |
| 65 | /* RP Control */ |
| 66 | { 0x0a024, 0x00000000, 0x00000b92 }, |
| 67 | /* HW RC6 Control */ |
| 68 | { 0x0a090, 0x00000000, 0x88040000 }, |
| 69 | /* Video Frequency Request */ |
| 70 | { 0x0a00c, 0x00000000, 0x08000000 }, |
| 71 | { 0 }, |
| 72 | }; |
| 73 | |
| 74 | static const struct gt_reg haswell_gt_lock[] = { |
| 75 | { 0x0a248, 0xffffffff, 0x80000000 }, |
| 76 | { 0x0a004, 0xffffffff, 0x00000010 }, |
| 77 | { 0x0a080, 0xffffffff, 0x00000004 }, |
| 78 | { 0x0a180, 0xffffffff, 0x80000000 }, |
| 79 | { 0 }, |
| 80 | }; |
| 81 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 82 | /* |
| 83 | * Some VGA option roms are used for several chipsets but they only have one PCI ID in their |
| 84 | * header. If we encounter such an option rom, we need to do the mapping ourselves. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 85 | */ |
| 86 | |
| 87 | u32 map_oprom_vendev(u32 vendev) |
| 88 | { |
Elyes HAOUAS | 69d658f | 2016-09-17 20:32:07 +0200 | [diff] [blame] | 89 | u32 new_vendev = vendev; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 90 | |
| 91 | switch (vendev) { |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 92 | case 0x80860402: /* GT1 Desktop */ |
| 93 | case 0x80860406: /* GT1 Mobile */ |
| 94 | case 0x8086040a: /* GT1 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 95 | case 0x80860a06: /* GT1 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 96 | |
| 97 | case 0x80860412: /* GT2 Desktop */ |
| 98 | case 0x80860416: /* GT2 Mobile */ |
| 99 | case 0x8086041a: /* GT2 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 100 | case 0x80860a16: /* GT2 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 101 | |
| 102 | case 0x80860422: /* GT3 Desktop */ |
| 103 | case 0x80860426: /* GT3 Mobile */ |
| 104 | case 0x8086042a: /* GT3 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 105 | case 0x80860a26: /* GT3 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 106 | |
Iru Cai | 12a13e1 | 2020-05-22 22:57:03 +0800 | [diff] [blame] | 107 | case 0x80860d22: /* GT3e Desktop */ |
| 108 | case 0x80860d16: /* GT1 Mobile 4+3 */ |
| 109 | case 0x80860d26: /* GT2 Mobile 4+3, GT3e Mobile */ |
| 110 | case 0x80860d36: /* GT3 Mobile 4+3 */ |
| 111 | |
Elyes HAOUAS | 69d658f | 2016-09-17 20:32:07 +0200 | [diff] [blame] | 112 | new_vendev = 0x80860406; /* GT1 Mobile */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 113 | break; |
| 114 | } |
| 115 | |
| 116 | return new_vendev; |
| 117 | } |
| 118 | |
| 119 | static struct resource *gtt_res = NULL; |
| 120 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 121 | u32 gtt_read(u32 reg) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 122 | { |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 123 | u32 val; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 124 | val = read32(res2mmio(gtt_res, reg, 0)); |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 125 | return val; |
| 126 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 127 | } |
| 128 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 129 | void gtt_write(u32 reg, u32 data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 130 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 131 | write32(res2mmio(gtt_res, reg, 0), data); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 132 | } |
| 133 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 134 | static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) |
| 135 | { |
| 136 | u32 val = gtt_read(reg); |
| 137 | val &= andmask; |
| 138 | val |= ormask; |
| 139 | gtt_write(reg, val); |
| 140 | } |
| 141 | |
| 142 | static inline void gtt_write_regs(const struct gt_reg *gt) |
| 143 | { |
| 144 | for (; gt && gt->reg; gt++) { |
| 145 | if (gt->andmask) |
| 146 | gtt_rmw(gt->reg, gt->andmask, gt->ormask); |
| 147 | else |
| 148 | gtt_write(gt->reg, gt->ormask); |
| 149 | } |
| 150 | } |
| 151 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 152 | #define GTT_RETRY 1000 |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 153 | int gtt_poll(u32 reg, u32 mask, u32 value) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 154 | { |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 155 | unsigned int try = GTT_RETRY; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 156 | u32 data; |
| 157 | |
| 158 | while (try--) { |
| 159 | data = gtt_read(reg); |
| 160 | if ((data & mask) == value) |
| 161 | return 1; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 162 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 163 | udelay(10); |
| 164 | } |
| 165 | |
| 166 | printk(BIOS_ERR, "GT init timeout\n"); |
| 167 | return 0; |
| 168 | } |
| 169 | |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 170 | static void power_well_enable(void) |
| 171 | { |
| 172 | gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); |
| 173 | gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE); |
| 174 | } |
| 175 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 176 | static void gma_pm_init_pre_vbios(struct device *dev) |
| 177 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 178 | printk(BIOS_DEBUG, "GT Power Management Init\n"); |
| 179 | |
| 180 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 181 | if (!gtt_res || !gtt_res->base) |
| 182 | return; |
| 183 | |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 184 | power_well_enable(); |
| 185 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 186 | /* |
| 187 | * Enable RC6 |
| 188 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 189 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 190 | /* Enable Force Wake */ |
| 191 | gtt_write(0x0a180, 1 << 5); |
| 192 | gtt_write(0x0a188, 0x00010001); |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 193 | gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 1 << 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 194 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 195 | /* GT Settings */ |
| 196 | gtt_write_regs(haswell_gt_setup); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 197 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 198 | /* Wait for Mailbox Ready */ |
Angel Pons | f5dd7b6 | 2020-10-24 12:24:19 +0200 | [diff] [blame] | 199 | gtt_poll(0x138124, (1 << 31), (0 << 31)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 200 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 201 | /* Mailbox Data - RC6 VIDS */ |
| 202 | gtt_write(0x138128, 0x00000000); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 203 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 204 | /* Mailbox Command */ |
| 205 | gtt_write(0x138124, 0x80000004); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 206 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 207 | /* Wait for Mailbox Ready */ |
Angel Pons | f5dd7b6 | 2020-10-24 12:24:19 +0200 | [diff] [blame] | 208 | gtt_poll(0x138124, (1 << 31), (0 << 31)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 209 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 210 | /* Enable PM Interrupts */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 211 | gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | |
| 212 | GEN6_PM_RP_DOWN_TIMEOUT | GEN6_PM_RP_UP_THRESHOLD | |
| 213 | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_UP_EI_EXPIRED | |
| 214 | GEN6_PM_RP_DOWN_EI_EXPIRED); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 215 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 216 | /* Enable RC6 in idle */ |
| 217 | gtt_write(0x0a094, 0x00040000); |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 218 | |
| 219 | /* PM Lock Settings */ |
| 220 | gtt_write_regs(haswell_gt_lock); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 221 | } |
| 222 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 223 | static void init_display_planes(void) |
| 224 | { |
| 225 | int pipe, plane; |
| 226 | |
| 227 | /* Disable cursor mode */ |
| 228 | for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) { |
| 229 | gtt_write(CURCNTR_IVB(pipe), CURSOR_MODE_DISABLE); |
| 230 | gtt_write(CURBASE_IVB(pipe), 0x00000000); |
| 231 | } |
| 232 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 233 | /* Disable primary plane and set surface base address */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 234 | for (plane = PLANE_A; plane <= PLANE_C; plane++) { |
| 235 | gtt_write(DSPCNTR(plane), DISPLAY_PLANE_DISABLE); |
| 236 | gtt_write(DSPSURF(plane), 0x00000000); |
| 237 | } |
| 238 | |
| 239 | /* Disable VGA display */ |
| 240 | gtt_write(CPU_VGACNTRL, CPU_VGA_DISABLE); |
| 241 | } |
| 242 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 243 | static void gma_setup_panel(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 244 | { |
Angel Pons | e153a35 | 2020-10-23 14:53:59 +0200 | [diff] [blame] | 245 | struct northbridge_intel_haswell_config *conf = config_of(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 246 | u32 reg32; |
| 247 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 248 | /* Setup Digital Port Hotplug */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 249 | reg32 = gtt_read(PCH_PORT_HOTPLUG); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 250 | if (!reg32) { |
| 251 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 252 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 253 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 254 | gtt_write(PCH_PORT_HOTPLUG, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | /* Setup Panel Power On Delays */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 258 | reg32 = gtt_read(PCH_PP_ON_DELAYS); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 259 | if (!reg32) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 260 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 261 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 262 | gtt_write(PCH_PP_ON_DELAYS, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | /* Setup Panel Power Off Delays */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 266 | reg32 = gtt_read(PCH_PP_OFF_DELAYS); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 267 | if (!reg32) { |
| 268 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 269 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 270 | gtt_write(PCH_PP_OFF_DELAYS, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | /* Setup Panel Power Cycle Delay */ |
| 274 | if (conf->gpu_panel_power_cycle_delay) { |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 275 | reg32 = gtt_read(PCH_PP_DIVISOR); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 276 | reg32 &= ~0xff; |
| 277 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 278 | gtt_write(PCH_PP_DIVISOR, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 279 | } |
| 280 | |
Nico Huber | c2e4642 | 2020-03-23 01:22:49 +0100 | [diff] [blame] | 281 | /* Enforce the PCH PWM function, as so does Linux. |
| 282 | The CPU PWM controls are disabled after reset. */ |
| 283 | if (conf->gpu_pch_backlight_pwm_hz) { |
| 284 | /* Reference clock is either 24MHz or 135MHz. We can choose |
| 285 | either a 16 or a 128 step increment. Use 16 if we would |
| 286 | have less than 100 steps otherwise. */ |
| 287 | const unsigned int refclock = CONFIG(INTEL_LYNXPOINT_LP) ? 24*MHz : 135*MHz; |
| 288 | const unsigned int hz_limit = refclock / 128 / 100; |
| 289 | unsigned int pwm_increment, pwm_period; |
| 290 | u32 south_chicken2; |
| 291 | |
| 292 | south_chicken2 = gtt_read(SOUTH_CHICKEN2); |
| 293 | if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { |
| 294 | pwm_increment = 16; |
| 295 | south_chicken2 |= LPT_PWM_GRANULARITY; |
| 296 | } else { |
| 297 | pwm_increment = 128; |
| 298 | south_chicken2 &= ~LPT_PWM_GRANULARITY; |
| 299 | } |
| 300 | gtt_write(SOUTH_CHICKEN2, south_chicken2); |
| 301 | |
| 302 | pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; |
| 303 | printk(BIOS_INFO, |
| 304 | "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n", |
| 305 | refclock / MHz, pwm_increment, pwm_period, |
| 306 | DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period)); |
| 307 | |
| 308 | /* Start with a 50% duty cycle. */ |
| 309 | gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); |
| 310 | |
| 311 | gtt_write(BLC_PWM_PCH_CTL1, |
| 312 | (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | |
| 313 | BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 314 | } |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 315 | |
| 316 | /* Get display,pipeline,and DDI registers into a basic sane state */ |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 317 | power_well_enable(); |
| 318 | |
| 319 | init_display_planes(); |
| 320 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 321 | /* |
| 322 | * DDI-A params set: |
| 323 | * bit 0: Display detected (RO) |
| 324 | * bit 4: DDI A supports 4 lanes and DDI E is not used |
| 325 | * bit 7: DDI buffer is idle |
| 326 | */ |
Tristan Corrick | 1a73eb0 | 2018-10-31 02:27:29 +1300 | [diff] [blame] | 327 | reg32 = DDI_BUF_IS_IDLE | DDI_INIT_DISPLAY_DETECTED; |
| 328 | if (!conf->gpu_ddi_e_connected) |
| 329 | reg32 |= DDI_A_4_LANES; |
| 330 | gtt_write(DDI_BUF_CTL_A, reg32); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 331 | |
| 332 | /* Set FDI registers - is this required? */ |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 333 | gtt_write(_FDI_RXA_MISC, 0x00200090); |
| 334 | gtt_write(_FDI_RXA_MISC, 0x0a000000); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 335 | |
| 336 | /* Enable the handshake with PCH display when processing reset */ |
| 337 | gtt_write(NDE_RSTWRN_OPT, RST_PCH_HNDSHK_EN); |
| 338 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 339 | /* Undocumented */ |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 340 | gtt_write(0x42090, 0x04000000); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 341 | gtt_write(0x9840, 0x00000000); |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 342 | gtt_write(0x42090, 0xa4000000); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 343 | |
| 344 | gtt_write(SOUTH_DSPCLK_GATE_D, PCH_LP_PARTITION_LEVEL_DISABLE); |
| 345 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 346 | /* Undocumented */ |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 347 | gtt_write(0x42080, 0x00004000); |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 348 | |
| 349 | /* Prepare DDI buffers for DP and FDI */ |
| 350 | intel_prepare_ddi(); |
| 351 | |
| 352 | /* Hot plug detect buffer enabled for port A */ |
| 353 | gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE); |
| 354 | |
| 355 | /* Enable HPD buffer for digital port D and B */ |
| 356 | gtt_write(PCH_PORT_HOTPLUG, PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE); |
| 357 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 358 | /* |
| 359 | * Bits 4:0 - Power cycle delay (default 0x6 --> 500ms) |
| 360 | * Bits 31:8 - Reference divider (0x0004af ----> 24MHz) |
| 361 | */ |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame] | 362 | gtt_write(PCH_PP_DIVISOR, 0x0004af06); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 363 | } |
| 364 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 365 | static void gma_pm_init_post_vbios(struct device *dev) |
| 366 | { |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 367 | int cdclk = 0; |
| 368 | int devid = pci_read_config16(dev, PCI_DEVICE_ID); |
| 369 | int gpu_is_ulx = 0; |
| 370 | |
| 371 | if (devid == 0x0a0e || devid == 0x0a1e) |
| 372 | gpu_is_ulx = 1; |
| 373 | |
| 374 | /* CD Frequency */ |
Duncan Laurie | 3106d0f | 2013-08-12 13:51:22 -0700 | [diff] [blame] | 375 | if ((gtt_read(0x42014) & 0x1000000) || gpu_is_ulx || haswell_is_ult()) |
| 376 | cdclk = 0; /* fixed frequency */ |
| 377 | else |
| 378 | cdclk = 2; /* variable frequency */ |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 379 | |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 380 | if (gpu_is_ulx || cdclk != 0) |
| 381 | gtt_rmw(0x130040, 0xf7ffffff, 0x04000000); |
| 382 | else |
| 383 | gtt_rmw(0x130040, 0xf3ffffff, 0x00000000); |
| 384 | |
| 385 | /* More magic */ |
| 386 | if (haswell_is_ult() || gpu_is_ulx) { |
Duncan Laurie | 3106d0f | 2013-08-12 13:51:22 -0700 | [diff] [blame] | 387 | if (!gpu_is_ulx) |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 388 | gtt_write(0x138128, 0x00000000); |
| 389 | else |
| 390 | gtt_write(0x138128, 0x00000001); |
| 391 | gtt_write(0x13812c, 0x00000000); |
| 392 | gtt_write(0x138124, 0x80000017); |
| 393 | } |
| 394 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 395 | /* Disable Force Wake */ |
| 396 | gtt_write(0x0a188, 0x00010000); |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 397 | gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 0 << 0); |
Duncan Laurie | 356833d | 2013-07-09 15:40:27 -0700 | [diff] [blame] | 398 | gtt_write(0x0a188, 0x00000001); |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 399 | } |
| 400 | |
Patrick Rudolph | 89f3a60 | 2017-06-20 18:25:22 +0200 | [diff] [blame] | 401 | /* Enable SCI to ACPI _GPE._L06 */ |
| 402 | static void gma_enable_swsci(void) |
| 403 | { |
| 404 | u16 reg16; |
| 405 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 406 | /* Clear DMISCI status */ |
Patrick Rudolph | 89f3a60 | 2017-06-20 18:25:22 +0200 | [diff] [blame] | 407 | reg16 = inw(get_pmbase() + TCO1_STS); |
| 408 | reg16 &= DMISCI_STS; |
| 409 | outw(get_pmbase() + TCO1_STS, reg16); |
| 410 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 411 | /* Clear and enable ACPI TCO SCI */ |
Patrick Rudolph | 89f3a60 | 2017-06-20 18:25:22 +0200 | [diff] [blame] | 412 | enable_tco_sci(); |
| 413 | } |
| 414 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 415 | static void gma_func0_init(struct device *dev) |
| 416 | { |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 417 | int lightup_ok = 0; |
Matt DeVillier | 6955b9c | 2017-04-16 01:42:44 -0500 | [diff] [blame] | 418 | |
Nico Huber | f2a0be2 | 2020-04-26 17:01:25 +0200 | [diff] [blame] | 419 | intel_gma_init_igd_opregion(); |
| 420 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 421 | /* Init graphics power management */ |
| 422 | gma_pm_init_pre_vbios(dev); |
| 423 | |
Matt DeVillier | 6955b9c | 2017-04-16 01:42:44 -0500 | [diff] [blame] | 424 | /* Pre panel init */ |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 425 | gma_setup_panel(dev); |
| 426 | |
Nico Huber | dd59762 | 2020-04-26 19:46:35 +0200 | [diff] [blame] | 427 | if (!CONFIG(NO_GFX_INIT)) |
| 428 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
| 429 | |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 430 | int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; |
| 431 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 432 | if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 433 | if (vga_disable) { |
| 434 | printk(BIOS_INFO, |
| 435 | "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); |
| 436 | } else { |
| 437 | printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); |
| 438 | gma_gfxinit(&lightup_ok); |
| 439 | gfx_set_init_done(1); |
| 440 | } |
Arthur Heymans | 23cda347 | 2016-12-18 16:03:52 +0100 | [diff] [blame] | 441 | } |
| 442 | |
Angel Pons | da59ca9 | 2020-10-23 14:59:37 +0200 | [diff] [blame] | 443 | if (!lightup_ok) { |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 444 | printk(BIOS_SPEW, "FUI did not run; using VBIOS\n"); |
Stefan Reinauer | f1aabec | 2014-01-22 15:16:30 -0800 | [diff] [blame] | 445 | mdelay(CONFIG_PRE_GRAPHICS_DELAY); |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 446 | pci_dev_init(dev); |
| 447 | } |
| 448 | |
Angel Pons | db3047c | 2020-10-23 14:56:19 +0200 | [diff] [blame] | 449 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 450 | |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 451 | gma_pm_init_post_vbios(dev); |
Patrick Rudolph | 89f3a60 | 2017-06-20 18:25:22 +0200 | [diff] [blame] | 452 | |
| 453 | gma_enable_swsci(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 454 | } |
| 455 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 456 | static void gma_generate_ssdt(const struct device *dev) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 457 | { |
Matt DeVillier | 41c4eb5 | 2020-03-30 19:20:54 -0500 | [diff] [blame] | 458 | const struct northbridge_intel_haswell_config *chip = dev->chip_info; |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 459 | |
Matt DeVillier | 41c4eb5 | 2020-03-30 19:20:54 -0500 | [diff] [blame] | 460 | drivers_intel_gma_displays_ssdt_generate(&chip->gfx); |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 461 | } |
| 462 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 463 | static struct device_operations gma_func0_ops = { |
Matt DeVillier | 41c4eb5 | 2020-03-30 19:20:54 -0500 | [diff] [blame] | 464 | .read_resources = pci_dev_read_resources, |
| 465 | .set_resources = pci_dev_set_resources, |
| 466 | .enable_resources = pci_dev_enable_resources, |
| 467 | .init = gma_func0_init, |
| 468 | .acpi_fill_ssdt = gma_generate_ssdt, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 469 | .ops_pci = &pci_dev_ops_pci, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 470 | }; |
| 471 | |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 472 | static const unsigned short pci_device_ids[] = { |
| 473 | 0x0402, /* Desktop GT1 */ |
| 474 | 0x0412, /* Desktop GT2 */ |
| 475 | 0x0422, /* Desktop GT3 */ |
Iru Cai | 12a13e1 | 2020-05-22 22:57:03 +0800 | [diff] [blame] | 476 | 0x0d22, /* Desktop GT3e */ |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 477 | 0x0406, /* Mobile GT1 */ |
| 478 | 0x0416, /* Mobile GT2 */ |
| 479 | 0x0426, /* Mobile GT3 */ |
| 480 | 0x0d16, /* Mobile 4+3 GT1 */ |
Iru Cai | 12a13e1 | 2020-05-22 22:57:03 +0800 | [diff] [blame] | 481 | 0x0d26, /* Mobile 4+3 GT2, Mobile GT3e */ |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 482 | 0x0d36, /* Mobile 4+3 GT3 */ |
| 483 | 0x0a06, /* ULT GT1 */ |
| 484 | 0x0a16, /* ULT GT2 */ |
| 485 | 0x0a26, /* ULT GT3 */ |
| 486 | 0, |
| 487 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 488 | |
| 489 | static const struct pci_driver pch_lpc __pci_driver = { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 490 | .ops = &gma_func0_ops, |
| 491 | .vendor = PCI_VENDOR_ID_INTEL, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 492 | .devices = pci_device_ids, |
| 493 | }; |