nb/intel/haswell: Add Crystal Well PCI IDs
From a log of a machine using Crystal Well CPU [1], Crystal Well CPUs
use some new PCI IDs. Without this patch, the Crystal Well northbridge
cannot be initialized in ramstage, thus the machine cannot boot. Some
PCI IDs of Crystal Well related devices can be found in the PCI ID
database [2].
Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. The board
boots to SeaBIOS with boot screen displayed on HDMI output, and then
boots Arch Linux on a USB disk.
[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/DNHLQTNTRQT43T67DG7L2HVI5CV74ZCM/
[2] https://pci-ids.ucw.cz/read/PC/8086
Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41658
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 68072ff..c466c09 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -108,6 +108,11 @@
case 0x8086042a: /* GT3 Server */
case 0x80860a26: /* GT3 ULT */
+ case 0x80860d22: /* GT3e Desktop */
+ case 0x80860d16: /* GT1 Mobile 4+3 */
+ case 0x80860d26: /* GT2 Mobile 4+3, GT3e Mobile */
+ case 0x80860d36: /* GT3 Mobile 4+3 */
+
new_vendev = 0x80860406; /* GT1 Mobile */
break;
}
@@ -515,11 +520,12 @@
0x0402, /* Desktop GT1 */
0x0412, /* Desktop GT2 */
0x0422, /* Desktop GT3 */
+ 0x0d22, /* Desktop GT3e */
0x0406, /* Mobile GT1 */
0x0416, /* Mobile GT2 */
0x0426, /* Mobile GT3 */
0x0d16, /* Mobile 4+3 GT1 */
- 0x0d26, /* Mobile 4+3 GT2 */
+ 0x0d26, /* Mobile 4+3 GT2, Mobile GT3e */
0x0d36, /* Mobile 4+3 GT3 */
0x0a06, /* ULT GT1 */
0x0a16, /* ULT GT2 */