Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 4 | * Copyright 2012 Google Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame^] | 26 | #include <drivers/intel/gma/i915_reg.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | |
| 28 | #include "chip.h" |
| 29 | #include "haswell.h" |
| 30 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 31 | /* some vga option roms are used for several chipsets but they only have one |
| 32 | * PCI ID in their header. If we encounter such an option rom, we need to do |
| 33 | * the mapping ourselfes |
| 34 | */ |
| 35 | |
| 36 | u32 map_oprom_vendev(u32 vendev) |
| 37 | { |
| 38 | u32 new_vendev=vendev; |
| 39 | |
| 40 | switch (vendev) { |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 41 | case 0x80860402: /* GT1 Desktop */ |
| 42 | case 0x80860406: /* GT1 Mobile */ |
| 43 | case 0x8086040a: /* GT1 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 44 | case 0x80860a06: /* GT1 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 45 | |
| 46 | case 0x80860412: /* GT2 Desktop */ |
| 47 | case 0x80860416: /* GT2 Mobile */ |
| 48 | case 0x8086041a: /* GT2 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 49 | case 0x80860a16: /* GT2 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 50 | |
| 51 | case 0x80860422: /* GT3 Desktop */ |
| 52 | case 0x80860426: /* GT3 Mobile */ |
| 53 | case 0x8086042a: /* GT3 Server */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 54 | case 0x80860a26: /* GT3 ULT */ |
Aaron Durbin | 7116129 | 2012-12-13 16:43:32 -0600 | [diff] [blame] | 55 | |
| 56 | new_vendev=0x80860406; /* GT1 Mobile */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 57 | break; |
| 58 | } |
| 59 | |
| 60 | return new_vendev; |
| 61 | } |
| 62 | |
| 63 | static struct resource *gtt_res = NULL; |
| 64 | |
| 65 | static inline u32 gtt_read(u32 reg) |
| 66 | { |
| 67 | return read32(gtt_res->base + reg); |
| 68 | } |
| 69 | |
| 70 | static inline void gtt_write(u32 reg, u32 data) |
| 71 | { |
| 72 | write32(gtt_res->base + reg, data); |
| 73 | } |
| 74 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 75 | #define GTT_RETRY 1000 |
| 76 | static int gtt_poll(u32 reg, u32 mask, u32 value) |
| 77 | { |
| 78 | unsigned try = GTT_RETRY; |
| 79 | u32 data; |
| 80 | |
| 81 | while (try--) { |
| 82 | data = gtt_read(reg); |
| 83 | if ((data & mask) == value) |
| 84 | return 1; |
| 85 | udelay(10); |
| 86 | } |
| 87 | |
| 88 | printk(BIOS_ERR, "GT init timeout\n"); |
| 89 | return 0; |
| 90 | } |
| 91 | |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame^] | 92 | static void power_well_enable(void) |
| 93 | { |
| 94 | gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); |
| 95 | gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE); |
| 96 | } |
| 97 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 98 | static void gma_pm_init_pre_vbios(struct device *dev) |
| 99 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 100 | printk(BIOS_DEBUG, "GT Power Management Init\n"); |
| 101 | |
| 102 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 103 | if (!gtt_res || !gtt_res->base) |
| 104 | return; |
| 105 | |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame^] | 106 | power_well_enable(); |
| 107 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 108 | /* |
| 109 | * Enable RC6 |
| 110 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 111 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 112 | /* Enable Force Wake */ |
| 113 | gtt_write(0x0a180, 1 << 5); |
| 114 | gtt_write(0x0a188, 0x00010001); |
| 115 | gtt_poll(0x130044, 1 << 0, 1 << 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 116 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 117 | /* Enable counters and lock */ |
| 118 | gtt_write(0x0a248, 0x80000016); |
| 119 | gtt_write(0x0a000, 0x00070020); |
| 120 | gtt_write(0x0a180, 0xc5000020); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 121 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 122 | /* Enable DOP clock gating */ |
| 123 | gtt_write(0x09424, 0x00000001); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 125 | /* Enable unit level clock gating */ |
| 126 | gtt_write(0x09400, 0x00000080); |
| 127 | gtt_write(0x09404, 0x40401000); |
| 128 | gtt_write(0x09408, 0x00000000); |
| 129 | gtt_write(0x0940c, 0x02000001); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 130 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 131 | /* Configure max ilde count */ |
| 132 | gtt_write(0x02054, 0x0000000a); |
| 133 | gtt_write(0x12054, 0x0000000a); |
| 134 | gtt_write(0x22054, 0x0000000a); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | |
Duncan Laurie | 990555b | 2013-05-10 11:00:07 -0700 | [diff] [blame] | 136 | gtt_write(0x0a008, 0x80000000); |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 137 | gtt_write(0x0a024, 0x00000b92); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 138 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 139 | /* Enable RC6 in idle */ |
| 140 | gtt_write(0x0a094, 0x00040000); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | } |
| 142 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 143 | static void gma_setup_panel(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 144 | { |
| 145 | struct northbridge_intel_haswell_config *conf = dev->chip_info; |
| 146 | u32 reg32; |
| 147 | |
| 148 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 149 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 150 | /* Setup Digital Port Hotplug */ |
| 151 | reg32 = gtt_read(0xc4030); |
| 152 | if (!reg32) { |
| 153 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 154 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 155 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 156 | gtt_write(0xc4030, reg32); |
| 157 | } |
| 158 | |
| 159 | /* Setup Panel Power On Delays */ |
| 160 | reg32 = gtt_read(0xc7208); |
| 161 | if (!reg32) { |
| 162 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 163 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 164 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 165 | gtt_write(0xc7208, reg32); |
| 166 | } |
| 167 | |
| 168 | /* Setup Panel Power Off Delays */ |
| 169 | reg32 = gtt_read(0xc720c); |
| 170 | if (!reg32) { |
| 171 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 172 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 173 | gtt_write(0xc720c, reg32); |
| 174 | } |
| 175 | |
| 176 | /* Setup Panel Power Cycle Delay */ |
| 177 | if (conf->gpu_panel_power_cycle_delay) { |
| 178 | reg32 = gtt_read(0xc7210); |
| 179 | reg32 &= ~0xff; |
| 180 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 181 | gtt_write(0xc7210, reg32); |
| 182 | } |
| 183 | |
| 184 | /* Enable Backlight if needed */ |
| 185 | if (conf->gpu_cpu_backlight) { |
| 186 | gtt_write(0x48250, (1 << 31)); |
| 187 | gtt_write(0x48254, conf->gpu_cpu_backlight); |
| 188 | } |
| 189 | if (conf->gpu_pch_backlight) { |
| 190 | gtt_write(0xc8250, (1 << 31)); |
| 191 | gtt_write(0xc8254, conf->gpu_pch_backlight); |
| 192 | } |
Ronald G. Minnich | 5bcca7e | 2013-06-25 15:56:46 -0700 | [diff] [blame^] | 193 | |
| 194 | /* Get display,pipeline,and DDI registers into a basic sane state */ |
| 195 | /* not all these have documented names. */ |
| 196 | gtt_write(0x45400, 0x80000000); |
| 197 | gtt_poll( 0x00045400, 0xc0000000, 0xc0000000); |
| 198 | gtt_write(_CURACNTR, 0x00000000); |
| 199 | gtt_write(_DSPACNTR, (/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000); |
| 200 | gtt_write(_DSPBCNTR, 0x00000000); |
| 201 | gtt_write(CPU_VGACNTRL, 0x8000298e); |
| 202 | gtt_write(_DSPASIZE+0xc, 0x00000000); |
| 203 | gtt_write(_DSPBSURF, 0x00000000); |
| 204 | gtt_write(0x4f008, 0x00000000); |
| 205 | gtt_write(0x4f008, 0x00000000); |
| 206 | gtt_write(0x4f008, 0x00000000); |
| 207 | gtt_write(0x4f040, 0x01000001); |
| 208 | gtt_write(0x4f044, 0x00000000); |
| 209 | gtt_write(0x4f048, 0x00000000); |
| 210 | gtt_write(0x4f04c, 0x03030000); |
| 211 | gtt_write(0x4f050, 0x00000000); |
| 212 | gtt_write(0x4f054, 0x00000001); |
| 213 | gtt_write(0x4f058, 0x00000000); |
| 214 | gtt_write(0x4f04c, 0x03450000); |
| 215 | gtt_write(0x4f04c, 0x45450000); |
| 216 | gtt_write(0x4f000, 0x03000400); |
| 217 | gtt_write(DP_A, 0x00000091); /* DDI-A enable */ |
| 218 | gtt_write(_FDI_RXA_MISC, 0x00200090); |
| 219 | gtt_write(_FDI_RXA_MISC, 0x0a000000); |
| 220 | gtt_write(0x46408, 0x00000070); |
| 221 | gtt_write(0x42090, 0x04000000); |
| 222 | gtt_write(0x4f050, 0xc0000000); |
| 223 | gtt_write(0x9840, 0x00000000); |
| 224 | gtt_write(0x42090, 0xa4000000); |
| 225 | gtt_write(SOUTH_DSPCLK_GATE_D, 0x00001000); |
| 226 | gtt_write(0x42080, 0x00004000); |
| 227 | gtt_write(0x64f80, 0x00ffffff); |
| 228 | gtt_write(0x64f84, 0x0007000e); |
| 229 | gtt_write(0x64f88, 0x00d75fff); |
| 230 | gtt_write(0x64f8c, 0x000f000a); |
| 231 | gtt_write(0x64f90, 0x00c30fff); |
| 232 | gtt_write(0x64f94, 0x00060006); |
| 233 | gtt_write(0x64f98, 0x00aaafff); |
| 234 | gtt_write(0x64f9c, 0x001e0000); |
| 235 | gtt_write(0x64fa0, 0x00ffffff); |
| 236 | gtt_write(0x64fa4, 0x000f000a); |
| 237 | gtt_write(0x64fa8, 0x00d75fff); |
| 238 | gtt_write(0x64fac, 0x00160004); |
| 239 | gtt_write(0x64fb0, 0x00c30fff); |
| 240 | gtt_write(0x64fb4, 0x001e0000); |
| 241 | gtt_write(0x64fb8, 0x00ffffff); |
| 242 | gtt_write(0x64fbc, 0x00060006); |
| 243 | gtt_write(0x64fc0, 0x00d75fff); |
| 244 | gtt_write(0x64fc4, 0x001e0000); |
| 245 | gtt_write(DDI_BUF_TRANS_A, 0x00ffffff); |
| 246 | gtt_write(DDI_BUF_TRANS_A+0x4, 0x0006000e); |
| 247 | gtt_write(DDI_BUF_TRANS_A+0x8, 0x00d75fff); |
| 248 | gtt_write(DDI_BUF_TRANS_A+0xc, 0x0005000a); |
| 249 | gtt_write(DDI_BUF_TRANS_A+0x10, 0x00c30fff); |
| 250 | gtt_write(DDI_BUF_TRANS_A+0x14, 0x00040006); |
| 251 | gtt_write(DDI_BUF_TRANS_A+0x18, 0x80aaafff); |
| 252 | gtt_write(DDI_BUF_TRANS_A+0x1c, 0x000b0000); |
| 253 | gtt_write(DDI_BUF_TRANS_A+0x20, 0x00ffffff); |
| 254 | gtt_write(DDI_BUF_TRANS_A+0x24, 0x0005000a); |
| 255 | gtt_write(DDI_BUF_TRANS_A+0x28, 0x00d75fff); |
| 256 | gtt_write(DDI_BUF_TRANS_A+0x2c, 0x000c0004); |
| 257 | gtt_write(DDI_BUF_TRANS_A+0x30, 0x80c30fff); |
| 258 | gtt_write(DDI_BUF_TRANS_A+0x34, 0x000b0000); |
| 259 | gtt_write(DDI_BUF_TRANS_A+0x38, 0x00ffffff); |
| 260 | gtt_write(DDI_BUF_TRANS_A+0x3c, 0x00040006); |
| 261 | gtt_write(DDI_BUF_TRANS_A+0x40, 0x80d75fff); |
| 262 | gtt_write(DDI_BUF_TRANS_A+0x44, 0x000b0000); |
| 263 | gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, |
| 264 | DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010); |
| 265 | gtt_write(SDEISR+0x30, |
| 266 | PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010); |
| 267 | gtt_write(PCH_PP_DIVISOR, 0x0004af06); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 268 | } |
| 269 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 270 | static void gma_pm_init_post_vbios(struct device *dev) |
| 271 | { |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 272 | /* Disable Force Wake */ |
| 273 | gtt_write(0x0a188, 0x00010000); |
| 274 | gtt_poll(0x130044, 1 << 0, 0 << 0); |
| 275 | } |
| 276 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 277 | static void gma_func0_init(struct device *dev) |
| 278 | { |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 279 | int lightup_ok = 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 280 | u32 reg32; |
Ronald G. Minnich | 2a66d6b | 2013-03-28 17:01:43 -0700 | [diff] [blame] | 281 | u32 graphics_base; //, graphics_size; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 282 | /* IGD needs to be Bus Master */ |
| 283 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 284 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 285 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 286 | |
Ronald G. Minnich | 2a66d6b | 2013-03-28 17:01:43 -0700 | [diff] [blame] | 287 | |
| 288 | /* the BAR for graphics space is a well known number for |
| 289 | * sandy and ivy. And the resource code renumbers it. |
| 290 | * So it's almost like having two hardcodes. |
| 291 | */ |
| 292 | graphics_base = dev->resource_list[1].base; |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 293 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 294 | /* Init graphics power management */ |
| 295 | gma_pm_init_pre_vbios(dev); |
| 296 | |
Duncan Laurie | c7f2ab7 | 2013-05-28 07:49:09 -0700 | [diff] [blame] | 297 | /* Post VBIOS init */ |
| 298 | gma_setup_panel(dev); |
| 299 | |
Ronald G. Minnich | 2a66d6b | 2013-03-28 17:01:43 -0700 | [diff] [blame] | 300 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 301 | printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); |
| 302 | u32 iobase, mmiobase, physbase; |
| 303 | iobase = dev->resource_list[2].base; |
| 304 | mmiobase = dev->resource_list[0].base; |
| 305 | physbase = pci_read_config32(dev, 0x5c) & ~0xf; |
| 306 | |
| 307 | int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 308 | lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base); |
Ronald G. Minnich | 2a66d6b | 2013-03-28 17:01:43 -0700 | [diff] [blame] | 309 | #endif |
Ronald G. Minnich | 4f78b18 | 2013-04-17 16:57:30 -0700 | [diff] [blame] | 310 | if (! lightup_ok) { |
| 311 | printk(BIOS_SPEW, "FUI did not run; using VBIOS\n"); |
| 312 | pci_dev_init(dev); |
| 313 | } |
| 314 | |
| 315 | /* Post VBIOS init */ |
| 316 | gma_pm_init_post_vbios(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 320 | { |
| 321 | if (!vendor || !device) { |
| 322 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 323 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 324 | } else { |
| 325 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 326 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 327 | } |
| 328 | } |
| 329 | |
Aaron Durbin | fcfe67c | 2013-03-22 22:23:05 -0500 | [diff] [blame] | 330 | static void gma_read_resources(struct device *dev) |
| 331 | { |
| 332 | pci_dev_read_resources(dev); |
| 333 | |
| 334 | #if CONFIG_MARK_GRAPHICS_MEM_WRCOMB |
| 335 | struct resource *res; |
| 336 | |
| 337 | /* Set the graphics memory to write combining. */ |
| 338 | res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 339 | if (res == NULL) { |
| 340 | printk(BIOS_DEBUG, "gma: memory resource not found.\n"); |
| 341 | return; |
| 342 | } |
| 343 | res->flags |= IORESOURCE_WRCOMB; |
| 344 | #endif |
| 345 | } |
| 346 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 347 | static struct pci_operations gma_pci_ops = { |
| 348 | .set_subsystem = gma_set_subsystem, |
| 349 | }; |
| 350 | |
| 351 | static struct device_operations gma_func0_ops = { |
Aaron Durbin | fcfe67c | 2013-03-22 22:23:05 -0500 | [diff] [blame] | 352 | .read_resources = gma_read_resources, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 353 | .set_resources = pci_dev_set_resources, |
| 354 | .enable_resources = pci_dev_enable_resources, |
| 355 | .init = gma_func0_init, |
| 356 | .scan_bus = 0, |
| 357 | .enable = 0, |
| 358 | .ops_pci = &gma_pci_ops, |
| 359 | }; |
| 360 | |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 361 | static const unsigned short pci_device_ids[] = { |
| 362 | 0x0402, /* Desktop GT1 */ |
| 363 | 0x0412, /* Desktop GT2 */ |
| 364 | 0x0422, /* Desktop GT3 */ |
| 365 | 0x0406, /* Mobile GT1 */ |
| 366 | 0x0416, /* Mobile GT2 */ |
| 367 | 0x0426, /* Mobile GT3 */ |
| 368 | 0x0d16, /* Mobile 4+3 GT1 */ |
| 369 | 0x0d26, /* Mobile 4+3 GT2 */ |
| 370 | 0x0d36, /* Mobile 4+3 GT3 */ |
| 371 | 0x0a06, /* ULT GT1 */ |
| 372 | 0x0a16, /* ULT GT2 */ |
| 373 | 0x0a26, /* ULT GT3 */ |
| 374 | 0, |
| 375 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 376 | |
| 377 | static const struct pci_driver pch_lpc __pci_driver = { |
| 378 | .ops = &gma_func0_ops, |
| 379 | .vendor = PCI_VENDOR_ID_INTEL, |
| 380 | .devices = pci_device_ids, |
| 381 | }; |