Angel Pons | 1ddb894 | 2020-04-04 18:51:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 3 | |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 4 | #include <arch/cache.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | #include <soc/clk.h> |
| 9 | #include <soc/cpu.h> |
| 10 | #include <soc/dp-core.h> |
| 11 | #include <soc/fimd.h> |
| 12 | #include <stddef.h> |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 13 | #include <string.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 14 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 15 | #include "chip.h" |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 16 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 17 | static unsigned int cpu_id; |
| 18 | static unsigned int cpu_rev; |
| 19 | |
| 20 | static void set_cpu_id(void) |
| 21 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 22 | cpu_id = read32((void *)EXYNOS5_PRO_ID); |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 23 | cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12)); |
| 24 | |
| 25 | /* |
| 26 | * 0xC200: EXYNOS4210 EVT0 |
| 27 | * 0xC210: EXYNOS4210 EVT1 |
| 28 | */ |
| 29 | if (cpu_id == 0xC200) { |
| 30 | cpu_id |= 0x10; |
| 31 | cpu_rev = 0; |
| 32 | } else if (cpu_id == 0xC210) { |
| 33 | cpu_rev = 1; |
| 34 | } |
| 35 | } |
| 36 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 37 | /* we distinguish a display port device from a raw graphics device |
| 38 | * because there are dramatic differences in startup depending on |
| 39 | * graphics usage. To make startup fast and easier to understand and |
| 40 | * debug we explicitly name this common case. The alternate approach, |
| 41 | * involving lots of machine and callbacks, is hard to debug and |
| 42 | * verify. |
| 43 | */ |
Elyes HAOUAS | 0111533 | 2018-05-25 09:15:21 +0200 | [diff] [blame] | 44 | static void exynos_displayport_init(struct device *dev, u32 lcdbase, |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 45 | unsigned long fb_size) |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 46 | { |
Hung-Te Lin | 22d0ca0 | 2013-09-27 12:45:45 +0800 | [diff] [blame] | 47 | struct soc_samsung_exynos5250_config *conf = dev->chip_info; |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 48 | /* put these on the stack. If, at some point, we want to move |
| 49 | * this code to a pre-ram stage, it will be much easier. |
| 50 | */ |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 51 | struct exynos5_fimd_panel panel; |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 52 | memset(&panel, 0, sizeof(panel)); |
| 53 | |
| 54 | panel.is_dp = 1; /* Display I/F is eDP */ |
| 55 | /* while it is true that we did a memset to zero, |
| 56 | * we leave some 'set to zero' entries here to make |
| 57 | * it clear what's going on. Graphics is confusing. |
| 58 | */ |
| 59 | panel.is_mipi = 0; |
| 60 | panel.fixvclk = 0; |
| 61 | panel.ivclk = 0; |
| 62 | panel.clkval_f = conf->clkval_f; |
| 63 | panel.upper_margin = conf->upper_margin; |
| 64 | panel.lower_margin = conf->lower_margin; |
| 65 | panel.vsync = conf->vsync; |
| 66 | panel.left_margin = conf->left_margin; |
| 67 | panel.right_margin = conf->right_margin; |
| 68 | panel.hsync = conf->hsync; |
Ronald G. Minnich | d83c117 | 2013-04-18 16:10:29 -0700 | [diff] [blame] | 69 | panel.xres = conf->xres; |
| 70 | panel.yres = conf->yres; |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 71 | |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 72 | printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); |
Gabe Black | 39fda6d | 2013-05-18 23:06:47 -0700 | [diff] [blame] | 73 | memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ |
| 74 | |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 75 | /* |
| 76 | * We need to clean and invalidate the framebuffer region and disable |
| 77 | * caching as well. We assume that our dcache <--> memory address |
| 78 | * space is identity-mapped in 1MB chunks, so align accordingly. |
| 79 | * |
| 80 | * Note: We may want to do something clever to ensure the framebuffer |
| 81 | * region is aligned such that we don't change dcache policy for other |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 82 | * stuff inadvertently. |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 83 | */ |
| 84 | uint32_t lower = ALIGN_DOWN(lcdbase, MiB); |
Gabe Black | 1e797bd | 2013-05-18 15:58:46 -0700 | [diff] [blame] | 85 | uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 86 | |
Julius Werner | f09f224 | 2013-08-28 14:43:14 -0700 | [diff] [blame] | 87 | dcache_clean_invalidate_by_mva((void *)lower, upper - lower); |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 88 | mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); |
| 89 | |
| 90 | printk(BIOS_DEBUG, "Initializing Exynos LCD.\n"); |
| 91 | |
Isaac Christensen | 0c0efa7 | 2014-09-17 16:14:18 -0600 | [diff] [blame] | 92 | lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 93 | } |
| 94 | |
Elyes HAOUAS | 0111533 | 2018-05-25 09:15:21 +0200 | [diff] [blame] | 95 | static void cpu_enable(struct device *dev) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 96 | { |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 97 | unsigned long fb_size = FB_SIZE_KB * KiB; |
| 98 | u32 lcdbase = get_fb_base_kb() * KiB; |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 99 | |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 100 | ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 101 | mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB)); |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 102 | |
| 103 | exynos_displayport_init(dev, lcdbase, fb_size); |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 104 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 105 | set_cpu_id(); |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 106 | } |
| 107 | |
Elyes HAOUAS | 0111533 | 2018-05-25 09:15:21 +0200 | [diff] [blame] | 108 | static void cpu_init(struct device *dev) |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 109 | { |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 110 | printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", |
| 111 | cpu_id, get_arm_clk() / (1024*1024)); |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 112 | } |
| 113 | |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 114 | static struct device_operations cpu_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame^] | 115 | .read_resources = noop_read_resources, |
| 116 | .set_resources = noop_set_resources, |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 117 | .enable_resources = cpu_enable, |
| 118 | .init = cpu_init, |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 119 | }; |
| 120 | |
Elyes HAOUAS | 0111533 | 2018-05-25 09:15:21 +0200 | [diff] [blame] | 121 | static void enable_exynos5250_dev(struct device *dev) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 122 | { |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 123 | dev->ops = &cpu_ops; |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 124 | } |
| 125 | |
Gabe Black | d81f409 | 2013-10-08 23:16:51 -0700 | [diff] [blame] | 126 | struct chip_operations soc_samsung_exynos5250_ops = { |
| 127 | CHIP_NAME("SOC Samsung Exynos 5250") |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 128 | .enable_dev = enable_exynos5250_dev, |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 129 | }; |
David Hendricks | c01d138 | 2013-03-28 19:04:58 -0700 | [diff] [blame] | 130 | |
| 131 | void exynos5250_config_l2_cache(void) |
| 132 | { |
| 133 | uint32_t val; |
| 134 | |
| 135 | /* |
| 136 | * Bit 9 - L2 tag RAM setup (1 cycle) |
| 137 | * Bits 8:6 - L2 tag RAM latency (3 cycles) |
| 138 | * Bit 5 - L2 data RAM setup (1 cycle) |
| 139 | * Bits 2:0 - L2 data RAM latency (3 cycles) |
| 140 | */ |
| 141 | val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); |
| 142 | write_l2ctlr(val); |
| 143 | } |