David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 1 | #include <console/console.h> |
| 2 | #include <device/device.h> |
David Hendricks | c01d138 | 2013-03-28 19:04:58 -0700 | [diff] [blame^] | 3 | #include <arch/cache.h> |
| 4 | #include <cpu/samsung/exynos5250/cpu.h> |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 5 | |
David Hendricks | 0f5a3fc | 2013-03-12 20:16:44 -0700 | [diff] [blame] | 6 | #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) |
| 7 | #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 8 | |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 9 | static void cpu_init(device_t dev) |
| 10 | { |
David Hendricks | 3cc0d1e | 2013-03-26 16:28:21 -0700 | [diff] [blame] | 11 | ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 12 | } |
| 13 | |
| 14 | static void cpu_noop(device_t dev) |
| 15 | { |
| 16 | } |
| 17 | |
| 18 | static struct device_operations cpu_ops = { |
| 19 | .read_resources = cpu_noop, |
| 20 | .set_resources = cpu_noop, |
| 21 | .enable_resources = cpu_noop, |
| 22 | .init = cpu_init, |
| 23 | .scan_bus = 0, |
| 24 | }; |
| 25 | |
David Hendricks | 0175587 | 2013-03-26 04:25:46 +0100 | [diff] [blame] | 26 | static void enable_dev(device_t dev) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 27 | { |
| 28 | /* Set the operations if it is a special bus type */ |
David Hendricks | 3cc0d1e | 2013-03-26 16:28:21 -0700 | [diff] [blame] | 29 | if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 30 | dev->ops = &cpu_ops; |
| 31 | } |
| 32 | } |
| 33 | |
| 34 | struct chip_operations cpu_samsung_exynos5250_ops = { |
| 35 | CHIP_NAME("CPU Samsung Exynos 5250") |
David Hendricks | 0175587 | 2013-03-26 04:25:46 +0100 | [diff] [blame] | 36 | .enable_dev = enable_dev, |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 37 | }; |
David Hendricks | c01d138 | 2013-03-28 19:04:58 -0700 | [diff] [blame^] | 38 | |
| 39 | void exynos5250_config_l2_cache(void) |
| 40 | { |
| 41 | uint32_t val; |
| 42 | |
| 43 | /* |
| 44 | * Bit 9 - L2 tag RAM setup (1 cycle) |
| 45 | * Bits 8:6 - L2 tag RAM latency (3 cycles) |
| 46 | * Bit 5 - L2 data RAM setup (1 cycle) |
| 47 | * Bits 2:0 - L2 data RAM latency (3 cycles) |
| 48 | */ |
| 49 | val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); |
| 50 | write_l2ctlr(val); |
| 51 | } |