Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * ACPI - create the Fixed ACPI Description Tables (FADT) |
| 5 | */ |
| 6 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 7 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 8 | #include <acpi/acpi.h> |
| 9 | #include <acpi/acpigen.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
| 11 | #include <arch/ioapic.h> |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 12 | #include <arch/smp/mpspec.h> |
Jason Glenesk | 498015d | 2020-12-10 03:28:38 -0800 | [diff] [blame] | 13 | #include <cpu/amd/cpuid.h> |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 14 | #include <cpu/amd/msr.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 15 | #include <cpu/x86/smm.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 16 | #include <device/device.h> |
| 17 | #include <device/pci.h> |
| 18 | #include <amdblocks/acpimmio.h> |
| 19 | #include <amdblocks/acpi.h> |
Raul E Rangel | 1c88b10 | 2021-02-11 10:35:32 -0700 | [diff] [blame] | 20 | #include <amdblocks/chip.h> |
Felix Held | dd2f3fa | 2021-02-08 22:23:54 +0100 | [diff] [blame] | 21 | #include <amdblocks/cpu.h> |
Felix Held | 604ffa6 | 2021-02-12 00:43:20 +0100 | [diff] [blame] | 22 | #include <amdblocks/ioapic.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 23 | #include <soc/acpi.h> |
| 24 | #include <soc/pci_devs.h> |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 25 | #include <soc/msr.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 26 | #include <soc/southbridge.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 27 | #include <soc/gpio.h> |
| 28 | #include <version.h> |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 29 | #include "chip.h" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 30 | |
| 31 | unsigned long acpi_fill_madt(unsigned long current) |
| 32 | { |
| 33 | /* create all subtables for processors */ |
| 34 | current = acpi_create_madt_lapics(current); |
| 35 | |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame^] | 36 | current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 37 | |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame^] | 38 | current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, |
| 39 | GNB_IO_APIC_ADDR); |
Jason Glenesk | f459a40 | 2020-09-02 16:49:10 -0700 | [diff] [blame] | 40 | |
Felix Held | 69a957f | 2021-06-17 15:48:25 +0200 | [diff] [blame] | 41 | /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ |
| 42 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, |
| 43 | MP_BUS_ISA, 0, 2, |
| 44 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); |
| 45 | /* SCI IRQ type override */ |
| 46 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, |
| 47 | MP_BUS_ISA, 9, 9, |
| 48 | MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 49 | |
Raul E Rangel | ffab5e6 | 2021-02-11 11:07:11 -0700 | [diff] [blame] | 50 | current = acpi_fill_madt_irqoverride(current); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 51 | |
| 52 | /* create all subtables for processors */ |
| 53 | current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, |
Felix Held | 69a957f | 2021-06-17 15:48:25 +0200 | [diff] [blame] | 54 | ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, |
| 55 | MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, |
| 56 | 1 /* 1: LINT1 connect to NMI */); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 57 | |
| 58 | return current; |
| 59 | } |
| 60 | |
| 61 | /* |
| 62 | * Reference section 5.2.9 Fixed ACPI Description Table (FADT) |
| 63 | * in the ACPI 3.0b specification. |
| 64 | */ |
Kyösti Mälkki | 61ef71b | 2020-05-30 18:54:39 +0300 | [diff] [blame] | 65 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 66 | { |
Raul E Rangel | 1c88b10 | 2021-02-11 10:35:32 -0700 | [diff] [blame] | 67 | const struct soc_amd_common_config *cfg = soc_get_common_config(); |
Martin Roth | eca8faa | 2019-12-01 16:49:19 -0700 | [diff] [blame] | 68 | |
Felix Held | 757d645 | 2021-02-04 21:31:49 +0100 | [diff] [blame] | 69 | printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 70 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 71 | fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ |
| 72 | |
Kyösti Mälkki | 0a9e72e | 2019-08-11 01:22:28 +0300 | [diff] [blame] | 73 | if (permanent_smi_handler()) { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 74 | fadt->smi_cmd = APM_CNT; |
| 75 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 76 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 80 | fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 81 | fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; |
| 82 | fadt->gpe0_blk = ACPI_GPE0_BLK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 83 | |
| 84 | fadt->pm1_evt_len = 4; /* 32 bits */ |
| 85 | fadt->pm1_cnt_len = 2; /* 16 bits */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 86 | fadt->pm_tmr_len = 4; /* 32 bits */ |
| 87 | fadt->gpe0_blk_len = 8; /* 64 bits */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 88 | |
Felix Held | 164c5ed | 2022-10-18 00:11:48 +0200 | [diff] [blame] | 89 | fill_fadt_extended_pm_regs(fadt); |
| 90 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 91 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 92 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 93 | fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ |
| 94 | fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ |
Felix Held | 72b92c9 | 2021-11-18 20:41:40 +0100 | [diff] [blame] | 95 | fadt->day_alrm = RTC_DATE_ALARM; |
Raul E Rangel | 041fcf5 | 2020-08-12 12:13:35 -0600 | [diff] [blame] | 96 | fadt->mon_alrm = 0; |
Martin Roth | eca8faa | 2019-12-01 16:49:19 -0700 | [diff] [blame] | 97 | fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 98 | fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ |
Martin Roth | eca8faa | 2019-12-01 16:49:19 -0700 | [diff] [blame] | 99 | fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ |
| 100 | ACPI_FADT_C1_SUPPORTED | |
| 101 | ACPI_FADT_S4_RTC_WAKE | |
| 102 | ACPI_FADT_32BIT_TIMER | |
| 103 | ACPI_FADT_PCI_EXPRESS_WAKE | |
| 104 | ACPI_FADT_PLATFORM_CLOCK | |
| 105 | ACPI_FADT_S4_RTC_VALID | |
| 106 | ACPI_FADT_REMOTE_POWER_ON; |
| 107 | fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 108 | |
Elyes Haouas | b55ac09 | 2022-02-16 14:42:19 +0100 | [diff] [blame] | 109 | fadt->ARM_boot_arch = 0; /* Must be zero if ACPI Revision <= 5.0 */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 110 | |
| 111 | fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ |
| 112 | fadt->x_firmware_ctl_h = 0; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 113 | } |
| 114 | |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 115 | static uint32_t get_pstate_core_freq(msr_t pstate_def) |
| 116 | { |
| 117 | uint32_t core_freq, core_freq_mul, core_freq_div; |
| 118 | bool valid_freq_divisor; |
| 119 | |
| 120 | /* Core frequency multiplier */ |
| 121 | core_freq_mul = pstate_def.lo & PSTATE_DEF_LO_FREQ_MUL_MASK; |
| 122 | |
| 123 | /* Core frequency divisor ID */ |
| 124 | core_freq_div = |
| 125 | (pstate_def.lo & PSTATE_DEF_LO_FREQ_DIV_MASK) >> PSTATE_DEF_LO_FREQ_DIV_SHIFT; |
| 126 | |
| 127 | if (core_freq_div == 0) { |
| 128 | return 0; |
| 129 | } else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN) |
| 130 | && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) { |
| 131 | /* Allow 1/8 integer steps for this range */ |
| 132 | valid_freq_divisor = 1; |
| 133 | } else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX) |
| 134 | && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { |
| 135 | /* Only allow 1/4 integer steps for this range */ |
| 136 | valid_freq_divisor = 1; |
| 137 | } else { |
| 138 | valid_freq_divisor = 0; |
| 139 | } |
| 140 | |
| 141 | if (valid_freq_divisor) { |
| 142 | /* 25 * core_freq_mul / (core_freq_div / 8) */ |
| 143 | core_freq = |
| 144 | ((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); |
| 145 | } else { |
| 146 | printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", |
| 147 | core_freq_div); |
| 148 | core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul); |
| 149 | } |
| 150 | return core_freq; |
| 151 | } |
| 152 | |
| 153 | static uint32_t get_pstate_core_power(msr_t pstate_def) |
| 154 | { |
| 155 | uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw; |
| 156 | |
| 157 | /* Core voltage ID */ |
| 158 | core_vid = |
| 159 | (pstate_def.lo & PSTATE_DEF_LO_CORE_VID_MASK) >> PSTATE_DEF_LO_CORE_VID_SHIFT; |
| 160 | |
| 161 | /* Current value in amps */ |
| 162 | current_value_amps = |
| 163 | (pstate_def.lo & PSTATE_DEF_LO_CUR_VAL_MASK) >> PSTATE_DEF_LO_CUR_VAL_SHIFT; |
| 164 | |
| 165 | /* Current divisor */ |
| 166 | current_divisor = |
| 167 | (pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT; |
| 168 | |
| 169 | /* Voltage */ |
| 170 | if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) { |
| 171 | /* Voltage off for VID codes 0xF8 to 0xFF */ |
| 172 | voltage_in_uvolts = 0; |
| 173 | } else { |
| 174 | voltage_in_uvolts = |
| 175 | SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid); |
| 176 | } |
| 177 | |
| 178 | /* Power in mW */ |
Zheng Bao | 62cd5e8 | 2022-08-25 17:11:38 +0800 | [diff] [blame] | 179 | power_in_mw = (voltage_in_uvolts) / 10 * current_value_amps; |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 180 | |
| 181 | switch (current_divisor) { |
| 182 | case 0: |
Zheng Bao | 62cd5e8 | 2022-08-25 17:11:38 +0800 | [diff] [blame] | 183 | power_in_mw = power_in_mw / 100L; |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 184 | break; |
| 185 | case 1: |
Zheng Bao | 62cd5e8 | 2022-08-25 17:11:38 +0800 | [diff] [blame] | 186 | power_in_mw = power_in_mw / 1000L; |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 187 | break; |
| 188 | case 2: |
Zheng Bao | 62cd5e8 | 2022-08-25 17:11:38 +0800 | [diff] [blame] | 189 | power_in_mw = power_in_mw / 10000L; |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 190 | break; |
| 191 | case 3: |
| 192 | /* current_divisor is set to an undefined value.*/ |
| 193 | printk(BIOS_WARNING, "Undefined current_divisor set for enabled P-state .\n"); |
| 194 | power_in_mw = 0; |
| 195 | break; |
| 196 | } |
| 197 | |
| 198 | return power_in_mw; |
| 199 | } |
| 200 | |
| 201 | /* |
| 202 | * Populate structure describing enabled p-states and return count of enabled p-states. |
| 203 | */ |
| 204 | static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, |
| 205 | struct acpi_xpss_sw_pstate *pstate_xpss_values) |
| 206 | { |
| 207 | msr_t pstate_def; |
| 208 | size_t pstate_count, pstate; |
| 209 | uint32_t pstate_enable, max_pstate; |
| 210 | |
| 211 | pstate_count = 0; |
| 212 | max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; |
| 213 | |
| 214 | for (pstate = 0; pstate <= max_pstate; pstate++) { |
| 215 | pstate_def = rdmsr(PSTATE_0_MSR + pstate); |
| 216 | |
| 217 | pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) |
| 218 | >> PSTATE_DEF_HI_ENABLE_SHIFT; |
| 219 | if (!pstate_enable) |
| 220 | continue; |
| 221 | |
| 222 | pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def); |
| 223 | pstate_values[pstate_count].power = get_pstate_core_power(pstate_def); |
| 224 | pstate_values[pstate_count].transition_latency = 0; |
| 225 | pstate_values[pstate_count].bus_master_latency = 0; |
| 226 | pstate_values[pstate_count].control_value = pstate; |
| 227 | pstate_values[pstate_count].status_value = pstate; |
| 228 | |
| 229 | pstate_xpss_values[pstate_count].core_freq = |
| 230 | (uint64_t)pstate_values[pstate_count].core_freq; |
| 231 | pstate_xpss_values[pstate_count].power = |
| 232 | (uint64_t)pstate_values[pstate_count].power; |
| 233 | pstate_xpss_values[pstate_count].transition_latency = 0; |
| 234 | pstate_xpss_values[pstate_count].bus_master_latency = 0; |
| 235 | pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate; |
| 236 | pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate; |
| 237 | pstate_count++; |
| 238 | } |
| 239 | |
| 240 | return pstate_count; |
| 241 | } |
| 242 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 243 | void generate_cpu_entries(const struct device *device) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 244 | { |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 245 | int logical_cores; |
| 246 | size_t pstate_count, cpu, proc_blk_len; |
| 247 | struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; |
| 248 | struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; |
| 249 | uint32_t threads_per_core, proc_blk_addr; |
| 250 | uint32_t cstate_base_address = |
| 251 | rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 252 | |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 253 | const acpi_addr_t perf_ctrl = { |
| 254 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 255 | .bit_width = 64, |
| 256 | .addrl = PS_CTL_REG, |
| 257 | }; |
| 258 | const acpi_addr_t perf_sts = { |
| 259 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 260 | .bit_width = 64, |
| 261 | .addrl = PS_STS_REG, |
| 262 | }; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 263 | |
Angel Pons | d2794ce | 2021-10-17 12:59:43 +0200 | [diff] [blame] | 264 | const acpi_cstate_t cstate_info[] = { |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 265 | [0] = { |
| 266 | .ctype = 1, |
| 267 | .latency = 1, |
| 268 | .power = 0, |
| 269 | .resource = { |
| 270 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 271 | .bit_width = 2, |
| 272 | .bit_offset = 2, |
| 273 | .addrl = 0, |
| 274 | .addrh = 0, |
| 275 | }, |
| 276 | }, |
| 277 | [1] = { |
| 278 | .ctype = 2, |
| 279 | .latency = 400, |
| 280 | .power = 0, |
| 281 | .resource = { |
| 282 | .space_id = ACPI_ADDRESS_SPACE_IO, |
| 283 | .bit_width = 8, |
| 284 | .bit_offset = 0, |
| 285 | .addrl = cstate_base_address + 1, |
| 286 | .addrh = 0, |
| 287 | .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, |
| 288 | }, |
| 289 | }, |
| 290 | }; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 291 | |
Felix Held | d4b5ad0 | 2022-01-25 04:14:05 +0100 | [diff] [blame] | 292 | threads_per_core = get_threads_per_core(); |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 293 | pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); |
| 294 | logical_cores = get_cpu_count(); |
| 295 | |
| 296 | for (cpu = 0; cpu < logical_cores; cpu++) { |
| 297 | |
| 298 | if (cpu == 0) { |
| 299 | /* BSP values for \_SB.Pxxx */ |
| 300 | proc_blk_len = 6; |
| 301 | proc_blk_addr = ACPI_GPE0_BLK; |
| 302 | } else { |
| 303 | /* AP values for \_SB.Pxxx */ |
| 304 | proc_blk_addr = 0; |
| 305 | proc_blk_len = 0; |
| 306 | } |
| 307 | |
| 308 | acpigen_write_processor(cpu, proc_blk_addr, proc_blk_len); |
| 309 | |
| 310 | acpigen_write_pct_package(&perf_ctrl, &perf_sts); |
| 311 | |
| 312 | acpigen_write_pss_object(pstate_values, pstate_count); |
| 313 | |
| 314 | acpigen_write_xpss_object(pstate_xpss_values, pstate_count); |
| 315 | |
| 316 | if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) |
| 317 | acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, |
| 318 | HW_ALL); |
| 319 | else |
| 320 | acpigen_write_PSD_package(0, logical_cores, SW_ALL); |
| 321 | |
| 322 | acpigen_write_PPC(0); |
| 323 | |
| 324 | acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info)); |
| 325 | |
Felix Held | c563508 | 2021-03-30 02:04:02 +0200 | [diff] [blame] | 326 | acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, |
| 327 | CSD_HW_ALL, 0); |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 328 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 329 | acpigen_pop_len(); |
| 330 | } |
Kyösti Mälkki | da321d8 | 2021-01-27 20:22:33 +0200 | [diff] [blame] | 331 | |
Felix Held | cf2eeff | 2022-03-02 15:00:59 +0100 | [diff] [blame] | 332 | acpigen_write_processor_package("PPKG", 0, logical_cores); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 333 | } |