Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 3 | |
| 4 | /* |
| 5 | * ACPI - create the Fixed ACPI Description Tables (FADT) |
| 6 | */ |
| 7 | |
| 8 | #include <string.h> |
| 9 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame^] | 10 | #include <acpi/acpi.h> |
| 11 | #include <acpi/acpigen.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 12 | #include <device/pci_ops.h> |
| 13 | #include <arch/ioapic.h> |
| 14 | #include <cpu/x86/smm.h> |
| 15 | #include <cbmem.h> |
| 16 | #include <device/device.h> |
| 17 | #include <device/pci.h> |
| 18 | #include <amdblocks/acpimmio.h> |
| 19 | #include <amdblocks/acpi.h> |
| 20 | #include <soc/acpi.h> |
| 21 | #include <soc/pci_devs.h> |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 22 | #include <soc/cpu.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 23 | #include <soc/southbridge.h> |
| 24 | #include <soc/northbridge.h> |
| 25 | #include <soc/nvs.h> |
| 26 | #include <soc/gpio.h> |
| 27 | #include <version.h> |
| 28 | |
| 29 | unsigned long acpi_fill_madt(unsigned long current) |
| 30 | { |
| 31 | /* create all subtables for processors */ |
| 32 | current = acpi_create_madt_lapics(current); |
| 33 | |
| 34 | /* Write Kern IOAPIC, only one */ |
| 35 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
| 36 | CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); |
| 37 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 38 | /* 0: mean bus 0--->ISA */ |
| 39 | /* 0: PIC 0 */ |
| 40 | /* 2: APIC 2 */ |
| 41 | /* 5 mean: 0101 --> Edge-triggered, Active high */ |
| 42 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 43 | current, 0, 0, 2, 0); |
| 44 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 45 | current, 0, 9, 9, 0xf); |
| 46 | |
| 47 | /* create all subtables for processors */ |
| 48 | current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, |
| 49 | 0xff, 5, 1); |
| 50 | /* 1: LINT1 connect to NMI */ |
| 51 | |
| 52 | return current; |
| 53 | } |
| 54 | |
| 55 | /* |
| 56 | * Reference section 5.2.9 Fixed ACPI Description Table (FADT) |
| 57 | * in the ACPI 3.0b specification. |
| 58 | */ |
| 59 | void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) |
| 60 | { |
| 61 | acpi_header_t *header = &(fadt->header); |
| 62 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 63 | printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 64 | |
| 65 | /* Prepare the header */ |
| 66 | memset((void *)fadt, 0, sizeof(acpi_fadt_t)); |
| 67 | memcpy(header->signature, "FACP", 4); |
| 68 | header->length = sizeof(acpi_fadt_t); |
| 69 | header->revision = get_acpi_table_revision(FADT); |
| 70 | memcpy(header->oem_id, OEM_ID, 6); |
| 71 | memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); |
| 72 | memcpy(header->asl_compiler_id, ASLC, 4); |
| 73 | header->asl_compiler_revision = asl_revision; |
| 74 | |
| 75 | fadt->firmware_ctrl = (u32) facs; |
| 76 | fadt->dsdt = (u32) dsdt; |
| 77 | fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ |
| 78 | fadt->preferred_pm_profile = FADT_PM_PROFILE; |
| 79 | fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ |
| 80 | |
| 81 | if (CONFIG(HAVE_SMI_HANDLER)) { |
| 82 | fadt->smi_cmd = APM_CNT; |
| 83 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 84 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 85 | fadt->s4bios_req = 0; /* Not supported */ |
| 86 | fadt->pstate_cnt = 0; /* Not supported */ |
| 87 | fadt->cst_cnt = 0; /* Not supported */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 88 | } else { |
| 89 | fadt->smi_cmd = 0; /* disable system management mode */ |
| 90 | fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ |
| 91 | fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ |
| 92 | fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ |
| 93 | fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ |
| 94 | fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; |
| 98 | fadt->pm1b_evt_blk = 0x0000; |
| 99 | fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; |
| 100 | fadt->pm1b_cnt_blk = 0x0000; |
| 101 | fadt->pm2_cnt_blk = 0x0000; |
| 102 | fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; |
| 103 | fadt->gpe0_blk = ACPI_GPE0_BLK; |
| 104 | fadt->gpe1_blk = 0x0000; /* No gpe1 block */ |
| 105 | |
| 106 | fadt->pm1_evt_len = 4; /* 32 bits */ |
| 107 | fadt->pm1_cnt_len = 2; /* 16 bits */ |
| 108 | fadt->pm2_cnt_len = 0; |
| 109 | fadt->pm_tmr_len = 4; /* 32 bits */ |
| 110 | fadt->gpe0_blk_len = 8; /* 64 bits */ |
| 111 | fadt->gpe1_blk_len = 0; |
| 112 | fadt->gpe1_base = 0; |
| 113 | |
| 114 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 115 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 116 | fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 117 | fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 118 | fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ |
| 119 | fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ |
| 120 | fadt->day_alrm = 0; /* 0x7d these have to be */ |
| 121 | fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ |
| 122 | fadt->century = 0; /* 0x7f to make rtc alarm work */ |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 123 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 124 | fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ |
| 125 | fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ |
| 126 | ACPI_FADT_C1_SUPPORTED | |
| 127 | ACPI_FADT_SLEEP_BUTTON | |
| 128 | ACPI_FADT_S4_RTC_WAKE | |
| 129 | ACPI_FADT_32BIT_TIMER | |
| 130 | ACPI_FADT_RESET_REGISTER | |
| 131 | ACPI_FADT_PCI_EXPRESS_WAKE | |
| 132 | ACPI_FADT_PLATFORM_CLOCK | |
| 133 | ACPI_FADT_S4_RTC_VALID | |
| 134 | ACPI_FADT_REMOTE_POWER_ON; |
| 135 | |
| 136 | /* Format is from 5.2.3.1: Generic Address Structure */ |
| 137 | /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ |
| 138 | /* 8 bit write of value 0x06 to 0xCF9 in IO space */ |
| 139 | fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
| 140 | fadt->reset_reg.bit_width = 8; |
| 141 | fadt->reset_reg.bit_offset = 0; |
| 142 | fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 143 | fadt->reset_reg.addrl = SYS_RESET; |
| 144 | fadt->reset_reg.addrh = 0x0; |
| 145 | |
| 146 | fadt->reset_value = 6; |
| 147 | |
| 148 | fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ |
| 149 | fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ |
| 150 | |
| 151 | fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ |
| 152 | fadt->x_firmware_ctl_h = 0; |
| 153 | fadt->x_dsdt_l = (u32) dsdt; |
| 154 | fadt->x_dsdt_h = 0; |
| 155 | |
| 156 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 157 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 158 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 159 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 160 | fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; |
| 161 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 162 | |
| 163 | fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 164 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 165 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 166 | fadt->x_pm1b_evt_blk.access_size = 0; |
| 167 | fadt->x_pm1b_evt_blk.addrl = 0x0; |
| 168 | fadt->x_pm1b_evt_blk.addrh = 0x0; |
| 169 | |
| 170 | |
| 171 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 172 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 173 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 174 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 175 | fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; |
| 176 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 177 | |
| 178 | fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 179 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 180 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 181 | fadt->x_pm1b_cnt_blk.access_size = 0; |
| 182 | fadt->x_pm1b_cnt_blk.addrl = 0x0; |
| 183 | fadt->x_pm1b_cnt_blk.addrh = 0x0; |
| 184 | |
| 185 | /* |
| 186 | * Note: Under this current AMD C state implementation, this is no |
| 187 | * longer used and should not be reported to OS. |
| 188 | */ |
| 189 | fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 190 | fadt->x_pm2_cnt_blk.bit_width = 0; |
| 191 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 192 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 193 | fadt->x_pm2_cnt_blk.addrl = 0; |
| 194 | fadt->x_pm2_cnt_blk.addrh = 0x0; |
| 195 | |
| 196 | |
| 197 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 198 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 199 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 200 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 201 | fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; |
| 202 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 203 | |
| 204 | |
| 205 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 206 | fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ |
| 207 | fadt->x_gpe0_blk.bit_offset = 0; |
| 208 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 209 | fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; |
| 210 | fadt->x_gpe0_blk.addrh = 0x0; |
| 211 | |
| 212 | |
| 213 | fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 214 | fadt->x_gpe1_blk.bit_width = 0; |
| 215 | fadt->x_gpe1_blk.bit_offset = 0; |
| 216 | fadt->x_gpe1_blk.access_size = 0; |
| 217 | fadt->x_gpe1_blk.addrl = 0; |
| 218 | fadt->x_gpe1_blk.addrh = 0x0; |
| 219 | |
| 220 | header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); |
| 221 | } |
| 222 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 223 | void generate_cpu_entries(const struct device *device) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 224 | { |
| 225 | int cores, cpu; |
| 226 | |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 227 | cores = get_cpu_count(); |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 228 | printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 229 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 230 | /* Generate BSP \_SB.P000 */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 231 | acpigen_write_processor(0, ACPI_GPE0_BLK, 6); |
| 232 | acpigen_pop_len(); |
| 233 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 234 | /* Generate AP \_SB.Pxxx */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 235 | for (cpu = 1; cpu < cores; cpu++) { |
| 236 | acpigen_write_processor(cpu, 0, 0); |
| 237 | acpigen_pop_len(); |
| 238 | } |
| 239 | } |
| 240 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 241 | unsigned long southbridge_write_acpi_tables(const struct device *device, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 242 | unsigned long current, |
| 243 | struct acpi_rsdp *rsdp) |
| 244 | { |
| 245 | return acpi_write_hpet(device, current, rsdp); |
| 246 | } |
| 247 | |
| 248 | static void acpi_create_gnvs(struct global_nvs_t *gnvs) |
| 249 | { |
| 250 | /* Clear out GNVS. */ |
| 251 | memset(gnvs, 0, sizeof(*gnvs)); |
| 252 | |
| 253 | if (CONFIG(CONSOLE_CBMEM)) |
| 254 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 255 | |
| 256 | if (CONFIG(CHROMEOS)) { |
| 257 | /* Initialize Verified Boot data */ |
| 258 | chromeos_init_chromeos_acpi(&gnvs->chromeos); |
| 259 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 260 | } |
| 261 | |
| 262 | /* Set unknown wake source */ |
| 263 | gnvs->pm1i = ~0ULL; |
| 264 | gnvs->gpei = ~0ULL; |
| 265 | |
| 266 | /* CPU core count */ |
| 267 | gnvs->pcnt = dev_count_cpu(); |
| 268 | } |
| 269 | |
Furquan Shaikh | 338fd9a | 2020-04-24 22:57:05 -0700 | [diff] [blame] | 270 | void southbridge_inject_dsdt(const struct device *device) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 271 | { |
| 272 | struct global_nvs_t *gnvs; |
| 273 | |
| 274 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 275 | |
| 276 | if (gnvs) { |
| 277 | acpi_create_gnvs(gnvs); |
| 278 | |
| 279 | /* Add it to DSDT */ |
| 280 | acpigen_write_scope("\\"); |
| 281 | acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); |
| 282 | acpigen_pop_len(); |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) |
| 287 | { |
| 288 | /* |
| 289 | * Store (\_SB.GPR2 (addr), Local5) |
| 290 | * \_SB.GPR2 is used to read control byte 2 from control register. |
| 291 | * / It is defined in gpio_lib.asl. |
| 292 | */ |
| 293 | acpigen_write_store(); |
| 294 | acpigen_emit_namestring("\\_SB.GPR2"); |
| 295 | acpigen_write_integer(addr); |
| 296 | acpigen_emit_byte(LOCAL5_OP); |
| 297 | } |
| 298 | |
| 299 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 300 | { |
| 301 | if (gpio_num >= SOC_GPIO_TOTAL_PINS) { |
| 302 | printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" |
| 303 | " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); |
| 304 | return -1; |
| 305 | } |
| 306 | uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); |
| 307 | |
| 308 | acpigen_soc_get_gpio_in_local5(addr); |
| 309 | |
| 310 | /* If (And (Local5, mask)) */ |
| 311 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 312 | |
| 313 | /* Store (One, Local0) */ |
| 314 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 315 | |
| 316 | acpigen_pop_len(); /* If */ |
| 317 | |
| 318 | /* Else */ |
| 319 | acpigen_write_else(); |
| 320 | |
| 321 | /* Store (Zero, Local0) */ |
| 322 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 323 | |
| 324 | acpigen_pop_len(); /* Else */ |
| 325 | |
| 326 | return 0; |
| 327 | } |
| 328 | |
| 329 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 330 | { |
| 331 | if (gpio_num >= SOC_GPIO_TOTAL_PINS) { |
| 332 | printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" |
| 333 | " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); |
| 334 | return -1; |
| 335 | } |
| 336 | uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); |
| 337 | |
| 338 | /* Store (0x40, Local0) */ |
| 339 | acpigen_write_store(); |
| 340 | acpigen_write_integer(GPIO_PIN_OUT); |
| 341 | acpigen_emit_byte(LOCAL0_OP); |
| 342 | |
| 343 | acpigen_soc_get_gpio_in_local5(addr); |
| 344 | |
| 345 | if (val) { |
| 346 | /* Or (Local5, GPIO_PIN_OUT, Local5) */ |
| 347 | acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); |
| 348 | } else { |
| 349 | /* Not (GPIO_PIN_OUT, Local6) */ |
| 350 | acpigen_write_not(LOCAL0_OP, LOCAL6_OP); |
| 351 | |
| 352 | /* And (Local5, Local6, Local5) */ |
| 353 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 354 | } |
| 355 | |
| 356 | /* |
| 357 | * SB.GPW2 (addr, Local5) |
| 358 | * \_SB.GPW2 is used to write control byte in control register |
| 359 | * / byte 2. It is defined in gpio_lib.asl. |
| 360 | */ |
| 361 | acpigen_emit_namestring("\\_SB.GPW2"); |
| 362 | acpigen_write_integer(addr); |
| 363 | acpigen_emit_byte(LOCAL5_OP); |
| 364 | |
| 365 | return 0; |
| 366 | } |
| 367 | |
| 368 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 369 | { |
| 370 | return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); |
| 371 | } |
| 372 | |
| 373 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 374 | { |
| 375 | return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); |
| 376 | } |
| 377 | |
| 378 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 379 | { |
| 380 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 381 | } |
| 382 | |
| 383 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 384 | { |
| 385 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 386 | } |