Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * ACPI - create the Fixed ACPI Description Tables (FADT) |
| 5 | */ |
| 6 | |
| 7 | #include <string.h> |
| 8 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 9 | #include <acpi/acpi.h> |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 10 | #include <acpi/acpi_gnvs.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 11 | #include <acpi/acpigen.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 12 | #include <device/pci_ops.h> |
| 13 | #include <arch/ioapic.h> |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 14 | #include <arch/smp/mpspec.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 15 | #include <cpu/x86/smm.h> |
| 16 | #include <cbmem.h> |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <amdblocks/acpimmio.h> |
| 20 | #include <amdblocks/acpi.h> |
| 21 | #include <soc/acpi.h> |
| 22 | #include <soc/pci_devs.h> |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 23 | #include <soc/cpu.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 24 | #include <soc/southbridge.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 25 | #include <soc/nvs.h> |
| 26 | #include <soc/gpio.h> |
| 27 | #include <version.h> |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 28 | #include "chip.h" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 29 | |
Raul E Rangel | 94acba8 | 2020-05-07 15:12:20 -0600 | [diff] [blame] | 30 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 31 | { |
| 32 | |
| 33 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 34 | CONFIG_MMCONF_BASE_ADDRESS, |
| 35 | 0, |
| 36 | 0, |
Aaron Durbin | 4a3a73c | 2020-06-12 16:44:50 -0600 | [diff] [blame] | 37 | CONFIG_MMCONF_BUS_NUMBER - 1); |
Raul E Rangel | 94acba8 | 2020-05-07 15:12:20 -0600 | [diff] [blame] | 38 | |
| 39 | return current; |
| 40 | } |
| 41 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 42 | unsigned long acpi_fill_madt(unsigned long current) |
| 43 | { |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 44 | const struct soc_amd_picasso_config *cfg = config_of_soc(); |
| 45 | unsigned int i; |
| 46 | uint8_t irq; |
| 47 | uint8_t flags; |
| 48 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 49 | /* create all subtables for processors */ |
| 50 | current = acpi_create_madt_lapics(current); |
| 51 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 52 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 53 | CONFIG_PICASSO_FCH_IOAPIC_ID, IO_APIC_ADDR, 0); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 54 | |
Jason Glenesk | f459a40 | 2020-09-02 16:49:10 -0700 | [diff] [blame^] | 55 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
| 56 | CONFIG_PICASSO_GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); |
| 57 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 58 | /* 0: mean bus 0--->ISA */ |
| 59 | /* 0: PIC 0 */ |
| 60 | /* 2: APIC 2 */ |
| 61 | /* 5 mean: 0101 --> Edge-triggered, Active high */ |
| 62 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 63 | current, 0, 0, 2, 0); |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 64 | current += acpi_create_madt_irqoverride( |
| 65 | (acpi_madt_irqoverride_t *)current, 0, 9, 9, |
| 66 | MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); |
| 67 | |
| 68 | for (i = 0; i < ARRAY_SIZE(cfg->irq_override); ++i) { |
| 69 | irq = cfg->irq_override[i].irq; |
| 70 | flags = cfg->irq_override[i].flags; |
| 71 | |
| 72 | if (!flags) |
| 73 | continue; |
| 74 | |
| 75 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, |
| 76 | irq, irq, flags); |
| 77 | } |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 78 | |
| 79 | /* create all subtables for processors */ |
| 80 | current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, |
| 81 | 0xff, 5, 1); |
| 82 | /* 1: LINT1 connect to NMI */ |
| 83 | |
| 84 | return current; |
| 85 | } |
| 86 | |
| 87 | /* |
| 88 | * Reference section 5.2.9 Fixed ACPI Description Table (FADT) |
| 89 | * in the ACPI 3.0b specification. |
| 90 | */ |
Kyösti Mälkki | 61ef71b | 2020-05-30 18:54:39 +0300 | [diff] [blame] | 91 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 92 | { |
Martin Roth | eca8faa | 2019-12-01 16:49:19 -0700 | [diff] [blame] | 93 | const struct soc_amd_picasso_config *cfg = config_of_soc(); |
| 94 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 95 | printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 96 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 97 | fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ |
| 98 | |
Kyösti Mälkki | 0a9e72e | 2019-08-11 01:22:28 +0300 | [diff] [blame] | 99 | if (permanent_smi_handler()) { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 100 | fadt->smi_cmd = APM_CNT; |
| 101 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 102 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 106 | fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 107 | fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; |
| 108 | fadt->gpe0_blk = ACPI_GPE0_BLK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 109 | |
| 110 | fadt->pm1_evt_len = 4; /* 32 bits */ |
| 111 | fadt->pm1_cnt_len = 2; /* 16 bits */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 112 | fadt->pm_tmr_len = 4; /* 32 bits */ |
| 113 | fadt->gpe0_blk_len = 8; /* 64 bits */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 114 | |
| 115 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 116 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 117 | fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ |
| 118 | fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ |
Raul E Rangel | 041fcf5 | 2020-08-12 12:13:35 -0600 | [diff] [blame] | 119 | fadt->day_alrm = 0x0d; |
| 120 | fadt->mon_alrm = 0; |
| 121 | fadt->century = 0x32; |
Martin Roth | eca8faa | 2019-12-01 16:49:19 -0700 | [diff] [blame] | 122 | fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 123 | fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ |
Martin Roth | eca8faa | 2019-12-01 16:49:19 -0700 | [diff] [blame] | 124 | fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ |
| 125 | ACPI_FADT_C1_SUPPORTED | |
| 126 | ACPI_FADT_S4_RTC_WAKE | |
| 127 | ACPI_FADT_32BIT_TIMER | |
| 128 | ACPI_FADT_PCI_EXPRESS_WAKE | |
| 129 | ACPI_FADT_PLATFORM_CLOCK | |
| 130 | ACPI_FADT_S4_RTC_VALID | |
| 131 | ACPI_FADT_REMOTE_POWER_ON; |
| 132 | fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 133 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 134 | fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ |
| 135 | fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ |
| 136 | |
| 137 | fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ |
| 138 | fadt->x_firmware_ctl_h = 0; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 139 | |
| 140 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 141 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 142 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 143 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 144 | fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; |
| 145 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 146 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 147 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 148 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 149 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 150 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 151 | fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; |
| 152 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 153 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 154 | |
| 155 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 156 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 157 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 158 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 159 | fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; |
| 160 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 161 | |
| 162 | |
| 163 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 164 | fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ |
| 165 | fadt->x_gpe0_blk.bit_offset = 0; |
Angel Pons | a23aff3 | 2020-06-21 20:47:54 +0200 | [diff] [blame] | 166 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 167 | fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; |
| 168 | fadt->x_gpe0_blk.addrh = 0x0; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 169 | } |
| 170 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 171 | void generate_cpu_entries(const struct device *device) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 172 | { |
| 173 | int cores, cpu; |
| 174 | |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 175 | cores = get_cpu_count(); |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 176 | printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 177 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 178 | /* Generate BSP \_SB.P000 */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 179 | acpigen_write_processor(0, ACPI_GPE0_BLK, 6); |
| 180 | acpigen_pop_len(); |
| 181 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 182 | /* Generate AP \_SB.Pxxx */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 183 | for (cpu = 1; cpu < cores; cpu++) { |
| 184 | acpigen_write_processor(cpu, 0, 0); |
| 185 | acpigen_pop_len(); |
| 186 | } |
| 187 | } |
| 188 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 189 | unsigned long southbridge_write_acpi_tables(const struct device *device, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 190 | unsigned long current, |
| 191 | struct acpi_rsdp *rsdp) |
| 192 | { |
| 193 | return acpi_write_hpet(device, current, rsdp); |
| 194 | } |
| 195 | |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 196 | void acpi_create_gnvs(struct global_nvs *gnvs) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 197 | { |
| 198 | /* Clear out GNVS. */ |
| 199 | memset(gnvs, 0, sizeof(*gnvs)); |
| 200 | |
| 201 | if (CONFIG(CONSOLE_CBMEM)) |
| 202 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 203 | |
| 204 | if (CONFIG(CHROMEOS)) { |
| 205 | /* Initialize Verified Boot data */ |
| 206 | chromeos_init_chromeos_acpi(&gnvs->chromeos); |
| 207 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 208 | } |
| 209 | |
| 210 | /* Set unknown wake source */ |
| 211 | gnvs->pm1i = ~0ULL; |
| 212 | gnvs->gpei = ~0ULL; |
| 213 | |
| 214 | /* CPU core count */ |
| 215 | gnvs->pcnt = dev_count_cpu(); |
| 216 | } |
| 217 | |
Furquan Shaikh | 338fd9a | 2020-04-24 22:57:05 -0700 | [diff] [blame] | 218 | void southbridge_inject_dsdt(const struct device *device) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 219 | { |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 220 | struct global_nvs *gnvs; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 221 | |
| 222 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 223 | |
| 224 | if (gnvs) { |
| 225 | acpi_create_gnvs(gnvs); |
| 226 | |
| 227 | /* Add it to DSDT */ |
| 228 | acpigen_write_scope("\\"); |
| 229 | acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); |
| 230 | acpigen_pop_len(); |
| 231 | } |
| 232 | } |
| 233 | |
| 234 | static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) |
| 235 | { |
| 236 | /* |
| 237 | * Store (\_SB.GPR2 (addr), Local5) |
| 238 | * \_SB.GPR2 is used to read control byte 2 from control register. |
| 239 | * / It is defined in gpio_lib.asl. |
| 240 | */ |
| 241 | acpigen_write_store(); |
| 242 | acpigen_emit_namestring("\\_SB.GPR2"); |
| 243 | acpigen_write_integer(addr); |
| 244 | acpigen_emit_byte(LOCAL5_OP); |
| 245 | } |
| 246 | |
| 247 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 248 | { |
| 249 | if (gpio_num >= SOC_GPIO_TOTAL_PINS) { |
| 250 | printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" |
| 251 | " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); |
| 252 | return -1; |
| 253 | } |
Kyösti Mälkki | 39bd46f | 2020-06-18 19:18:21 +0300 | [diff] [blame] | 254 | uintptr_t addr = gpio_get_address(gpio_num); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 255 | |
| 256 | acpigen_soc_get_gpio_in_local5(addr); |
| 257 | |
| 258 | /* If (And (Local5, mask)) */ |
| 259 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 260 | |
| 261 | /* Store (One, Local0) */ |
| 262 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 263 | |
| 264 | acpigen_pop_len(); /* If */ |
| 265 | |
| 266 | /* Else */ |
| 267 | acpigen_write_else(); |
| 268 | |
| 269 | /* Store (Zero, Local0) */ |
| 270 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 271 | |
| 272 | acpigen_pop_len(); /* Else */ |
| 273 | |
| 274 | return 0; |
| 275 | } |
| 276 | |
| 277 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 278 | { |
| 279 | if (gpio_num >= SOC_GPIO_TOTAL_PINS) { |
| 280 | printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" |
| 281 | " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); |
| 282 | return -1; |
| 283 | } |
Kyösti Mälkki | 39bd46f | 2020-06-18 19:18:21 +0300 | [diff] [blame] | 284 | uintptr_t addr = gpio_get_address(gpio_num); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 285 | |
| 286 | /* Store (0x40, Local0) */ |
| 287 | acpigen_write_store(); |
| 288 | acpigen_write_integer(GPIO_PIN_OUT); |
| 289 | acpigen_emit_byte(LOCAL0_OP); |
| 290 | |
| 291 | acpigen_soc_get_gpio_in_local5(addr); |
| 292 | |
| 293 | if (val) { |
| 294 | /* Or (Local5, GPIO_PIN_OUT, Local5) */ |
| 295 | acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); |
| 296 | } else { |
| 297 | /* Not (GPIO_PIN_OUT, Local6) */ |
| 298 | acpigen_write_not(LOCAL0_OP, LOCAL6_OP); |
| 299 | |
| 300 | /* And (Local5, Local6, Local5) */ |
| 301 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 302 | } |
| 303 | |
| 304 | /* |
| 305 | * SB.GPW2 (addr, Local5) |
| 306 | * \_SB.GPW2 is used to write control byte in control register |
| 307 | * / byte 2. It is defined in gpio_lib.asl. |
| 308 | */ |
| 309 | acpigen_emit_namestring("\\_SB.GPW2"); |
| 310 | acpigen_write_integer(addr); |
| 311 | acpigen_emit_byte(LOCAL5_OP); |
| 312 | |
| 313 | return 0; |
| 314 | } |
| 315 | |
| 316 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 317 | { |
| 318 | return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); |
| 319 | } |
| 320 | |
| 321 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 322 | { |
| 323 | return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); |
| 324 | } |
| 325 | |
| 326 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 327 | { |
| 328 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 329 | } |
| 330 | |
| 331 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 332 | { |
| 333 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 334 | } |