Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * ACPI - create the Fixed ACPI Description Tables (FADT) |
| 5 | */ |
| 6 | |
| 7 | #include <string.h> |
| 8 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 9 | #include <acpi/acpi.h> |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 10 | #include <acpi/acpi_gnvs.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 11 | #include <acpi/acpigen.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 12 | #include <device/pci_ops.h> |
| 13 | #include <arch/ioapic.h> |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 14 | #include <arch/smp/mpspec.h> |
Jason Glenesk | 498015d | 2020-12-10 03:28:38 -0800 | [diff] [blame^] | 15 | #include <cpu/amd/cpuid.h> |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 16 | #include <cpu/amd/msr.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 17 | #include <cpu/x86/smm.h> |
| 18 | #include <cbmem.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <amdblocks/acpimmio.h> |
| 22 | #include <amdblocks/acpi.h> |
| 23 | #include <soc/acpi.h> |
| 24 | #include <soc/pci_devs.h> |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 25 | #include <soc/cpu.h> |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 26 | #include <soc/msr.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 27 | #include <soc/southbridge.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 28 | #include <soc/nvs.h> |
| 29 | #include <soc/gpio.h> |
| 30 | #include <version.h> |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 31 | #include "chip.h" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 32 | |
Raul E Rangel | 94acba8 | 2020-05-07 15:12:20 -0600 | [diff] [blame] | 33 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 34 | { |
| 35 | |
| 36 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 37 | CONFIG_MMCONF_BASE_ADDRESS, |
| 38 | 0, |
| 39 | 0, |
Aaron Durbin | 4a3a73c | 2020-06-12 16:44:50 -0600 | [diff] [blame] | 40 | CONFIG_MMCONF_BUS_NUMBER - 1); |
Raul E Rangel | 94acba8 | 2020-05-07 15:12:20 -0600 | [diff] [blame] | 41 | |
| 42 | return current; |
| 43 | } |
| 44 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 45 | unsigned long acpi_fill_madt(unsigned long current) |
| 46 | { |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 47 | const struct soc_amd_picasso_config *cfg = config_of_soc(); |
| 48 | unsigned int i; |
| 49 | uint8_t irq; |
| 50 | uint8_t flags; |
| 51 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 52 | /* create all subtables for processors */ |
| 53 | current = acpi_create_madt_lapics(current); |
| 54 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 55 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 56 | CONFIG_PICASSO_FCH_IOAPIC_ID, IO_APIC_ADDR, 0); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 57 | |
Jason Glenesk | f459a40 | 2020-09-02 16:49:10 -0700 | [diff] [blame] | 58 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
| 59 | CONFIG_PICASSO_GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); |
| 60 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 61 | /* 0: mean bus 0--->ISA */ |
| 62 | /* 0: PIC 0 */ |
| 63 | /* 2: APIC 2 */ |
| 64 | /* 5 mean: 0101 --> Edge-triggered, Active high */ |
| 65 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 66 | current, 0, 0, 2, 0); |
Raul E Rangel | 93b62e6 | 2020-01-31 12:53:45 -0700 | [diff] [blame] | 67 | current += acpi_create_madt_irqoverride( |
| 68 | (acpi_madt_irqoverride_t *)current, 0, 9, 9, |
| 69 | MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); |
| 70 | |
| 71 | for (i = 0; i < ARRAY_SIZE(cfg->irq_override); ++i) { |
| 72 | irq = cfg->irq_override[i].irq; |
| 73 | flags = cfg->irq_override[i].flags; |
| 74 | |
| 75 | if (!flags) |
| 76 | continue; |
| 77 | |
| 78 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, |
| 79 | irq, irq, flags); |
| 80 | } |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 81 | |
| 82 | /* create all subtables for processors */ |
| 83 | current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, |
| 84 | 0xff, 5, 1); |
| 85 | /* 1: LINT1 connect to NMI */ |
| 86 | |
| 87 | return current; |
| 88 | } |
| 89 | |
| 90 | /* |
| 91 | * Reference section 5.2.9 Fixed ACPI Description Table (FADT) |
| 92 | * in the ACPI 3.0b specification. |
| 93 | */ |
Kyösti Mälkki | 61ef71b | 2020-05-30 18:54:39 +0300 | [diff] [blame] | 94 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 95 | { |
Martin Roth | eca8faa | 2019-12-01 16:49:19 -0700 | [diff] [blame] | 96 | const struct soc_amd_picasso_config *cfg = config_of_soc(); |
| 97 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 98 | printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 99 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 100 | fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ |
| 101 | |
Kyösti Mälkki | 0a9e72e | 2019-08-11 01:22:28 +0300 | [diff] [blame] | 102 | if (permanent_smi_handler()) { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 103 | fadt->smi_cmd = APM_CNT; |
| 104 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 105 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 109 | fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 110 | fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; |
| 111 | fadt->gpe0_blk = ACPI_GPE0_BLK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 112 | |
| 113 | fadt->pm1_evt_len = 4; /* 32 bits */ |
| 114 | fadt->pm1_cnt_len = 2; /* 16 bits */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 115 | fadt->pm_tmr_len = 4; /* 32 bits */ |
| 116 | fadt->gpe0_blk_len = 8; /* 64 bits */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 117 | |
| 118 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 119 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 120 | fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ |
| 121 | fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ |
Raul E Rangel | 041fcf5 | 2020-08-12 12:13:35 -0600 | [diff] [blame] | 122 | fadt->day_alrm = 0x0d; |
| 123 | fadt->mon_alrm = 0; |
| 124 | fadt->century = 0x32; |
Martin Roth | eca8faa | 2019-12-01 16:49:19 -0700 | [diff] [blame] | 125 | fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 126 | fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ |
Martin Roth | eca8faa | 2019-12-01 16:49:19 -0700 | [diff] [blame] | 127 | fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ |
| 128 | ACPI_FADT_C1_SUPPORTED | |
| 129 | ACPI_FADT_S4_RTC_WAKE | |
| 130 | ACPI_FADT_32BIT_TIMER | |
| 131 | ACPI_FADT_PCI_EXPRESS_WAKE | |
| 132 | ACPI_FADT_PLATFORM_CLOCK | |
| 133 | ACPI_FADT_S4_RTC_VALID | |
| 134 | ACPI_FADT_REMOTE_POWER_ON; |
| 135 | fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 136 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 137 | fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ |
| 138 | fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ |
| 139 | |
| 140 | fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ |
| 141 | fadt->x_firmware_ctl_h = 0; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 142 | |
| 143 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 144 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 145 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 146 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 147 | fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; |
| 148 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 149 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 150 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 151 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 152 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 153 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 154 | fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; |
| 155 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 156 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 157 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 158 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 159 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 160 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 161 | fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; |
| 162 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 163 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 164 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 165 | fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ |
| 166 | fadt->x_gpe0_blk.bit_offset = 0; |
Angel Pons | a23aff3 | 2020-06-21 20:47:54 +0200 | [diff] [blame] | 167 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 168 | fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; |
| 169 | fadt->x_gpe0_blk.addrh = 0x0; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 170 | } |
| 171 | |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 172 | static uint32_t get_pstate_core_freq(msr_t pstate_def) |
| 173 | { |
| 174 | uint32_t core_freq, core_freq_mul, core_freq_div; |
| 175 | bool valid_freq_divisor; |
| 176 | |
| 177 | /* Core frequency multiplier */ |
| 178 | core_freq_mul = pstate_def.lo & PSTATE_DEF_LO_FREQ_MUL_MASK; |
| 179 | |
| 180 | /* Core frequency divisor ID */ |
| 181 | core_freq_div = |
| 182 | (pstate_def.lo & PSTATE_DEF_LO_FREQ_DIV_MASK) >> PSTATE_DEF_LO_FREQ_DIV_SHIFT; |
| 183 | |
| 184 | if (core_freq_div == 0) { |
| 185 | return 0; |
| 186 | } else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN) |
| 187 | && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) { |
| 188 | /* Allow 1/8 integer steps for this range */ |
| 189 | valid_freq_divisor = 1; |
| 190 | } else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX) |
| 191 | && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { |
| 192 | /* Only allow 1/4 integer steps for this range */ |
| 193 | valid_freq_divisor = 1; |
| 194 | } else { |
| 195 | valid_freq_divisor = 0; |
| 196 | } |
| 197 | |
| 198 | if (valid_freq_divisor) { |
| 199 | /* 25 * core_freq_mul / (core_freq_div / 8) */ |
| 200 | core_freq = |
| 201 | ((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); |
| 202 | } else { |
| 203 | printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", |
| 204 | core_freq_div); |
| 205 | core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul); |
| 206 | } |
| 207 | return core_freq; |
| 208 | } |
| 209 | |
| 210 | static uint32_t get_pstate_core_power(msr_t pstate_def) |
| 211 | { |
| 212 | uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw; |
| 213 | |
| 214 | /* Core voltage ID */ |
| 215 | core_vid = |
| 216 | (pstate_def.lo & PSTATE_DEF_LO_CORE_VID_MASK) >> PSTATE_DEF_LO_CORE_VID_SHIFT; |
| 217 | |
| 218 | /* Current value in amps */ |
| 219 | current_value_amps = |
| 220 | (pstate_def.lo & PSTATE_DEF_LO_CUR_VAL_MASK) >> PSTATE_DEF_LO_CUR_VAL_SHIFT; |
| 221 | |
| 222 | /* Current divisor */ |
| 223 | current_divisor = |
| 224 | (pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT; |
| 225 | |
| 226 | /* Voltage */ |
| 227 | if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) { |
| 228 | /* Voltage off for VID codes 0xF8 to 0xFF */ |
| 229 | voltage_in_uvolts = 0; |
| 230 | } else { |
| 231 | voltage_in_uvolts = |
| 232 | SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid); |
| 233 | } |
| 234 | |
| 235 | /* Power in mW */ |
| 236 | power_in_mw = (voltage_in_uvolts) / 1000 * current_value_amps; |
| 237 | |
| 238 | switch (current_divisor) { |
| 239 | case 0: |
| 240 | break; |
| 241 | case 1: |
| 242 | power_in_mw = power_in_mw / 10L; |
| 243 | break; |
| 244 | case 2: |
| 245 | power_in_mw = power_in_mw / 100L; |
| 246 | break; |
| 247 | case 3: |
| 248 | /* current_divisor is set to an undefined value.*/ |
| 249 | printk(BIOS_WARNING, "Undefined current_divisor set for enabled P-state .\n"); |
| 250 | power_in_mw = 0; |
| 251 | break; |
| 252 | } |
| 253 | |
| 254 | return power_in_mw; |
| 255 | } |
| 256 | |
| 257 | /* |
| 258 | * Populate structure describing enabled p-states and return count of enabled p-states. |
| 259 | */ |
| 260 | static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, |
| 261 | struct acpi_xpss_sw_pstate *pstate_xpss_values) |
| 262 | { |
| 263 | msr_t pstate_def; |
| 264 | size_t pstate_count, pstate; |
| 265 | uint32_t pstate_enable, max_pstate; |
| 266 | |
| 267 | pstate_count = 0; |
| 268 | max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; |
| 269 | |
| 270 | for (pstate = 0; pstate <= max_pstate; pstate++) { |
| 271 | pstate_def = rdmsr(PSTATE_0_MSR + pstate); |
| 272 | |
| 273 | pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) |
| 274 | >> PSTATE_DEF_HI_ENABLE_SHIFT; |
| 275 | if (!pstate_enable) |
| 276 | continue; |
| 277 | |
| 278 | pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def); |
| 279 | pstate_values[pstate_count].power = get_pstate_core_power(pstate_def); |
| 280 | pstate_values[pstate_count].transition_latency = 0; |
| 281 | pstate_values[pstate_count].bus_master_latency = 0; |
| 282 | pstate_values[pstate_count].control_value = pstate; |
| 283 | pstate_values[pstate_count].status_value = pstate; |
| 284 | |
| 285 | pstate_xpss_values[pstate_count].core_freq = |
| 286 | (uint64_t)pstate_values[pstate_count].core_freq; |
| 287 | pstate_xpss_values[pstate_count].power = |
| 288 | (uint64_t)pstate_values[pstate_count].power; |
| 289 | pstate_xpss_values[pstate_count].transition_latency = 0; |
| 290 | pstate_xpss_values[pstate_count].bus_master_latency = 0; |
| 291 | pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate; |
| 292 | pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate; |
| 293 | pstate_count++; |
| 294 | } |
| 295 | |
| 296 | return pstate_count; |
| 297 | } |
| 298 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 299 | void generate_cpu_entries(const struct device *device) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 300 | { |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 301 | int logical_cores; |
| 302 | size_t pstate_count, cpu, proc_blk_len; |
| 303 | struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; |
| 304 | struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; |
| 305 | uint32_t threads_per_core, proc_blk_addr; |
| 306 | uint32_t cstate_base_address = |
| 307 | rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 308 | |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 309 | const acpi_addr_t perf_ctrl = { |
| 310 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 311 | .bit_width = 64, |
| 312 | .addrl = PS_CTL_REG, |
| 313 | }; |
| 314 | const acpi_addr_t perf_sts = { |
| 315 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 316 | .bit_width = 64, |
| 317 | .addrl = PS_STS_REG, |
| 318 | }; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 319 | |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 320 | acpi_cstate_t cstate_info[] = { |
| 321 | [0] = { |
| 322 | .ctype = 1, |
| 323 | .latency = 1, |
| 324 | .power = 0, |
| 325 | .resource = { |
| 326 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 327 | .bit_width = 2, |
| 328 | .bit_offset = 2, |
| 329 | .addrl = 0, |
| 330 | .addrh = 0, |
| 331 | }, |
| 332 | }, |
| 333 | [1] = { |
| 334 | .ctype = 2, |
| 335 | .latency = 400, |
| 336 | .power = 0, |
| 337 | .resource = { |
| 338 | .space_id = ACPI_ADDRESS_SPACE_IO, |
| 339 | .bit_width = 8, |
| 340 | .bit_offset = 0, |
| 341 | .addrl = cstate_base_address + 1, |
| 342 | .addrh = 0, |
| 343 | .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, |
| 344 | }, |
| 345 | }, |
| 346 | }; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 347 | |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 348 | threads_per_core = ((cpuid_ebx(CPUID_EBX_CORE_ID) & CPUID_EBX_THREADS_MASK) |
| 349 | >> CPUID_EBX_THREADS_SHIFT) |
| 350 | + 1; |
| 351 | pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); |
| 352 | logical_cores = get_cpu_count(); |
| 353 | |
| 354 | for (cpu = 0; cpu < logical_cores; cpu++) { |
| 355 | |
| 356 | if (cpu == 0) { |
| 357 | /* BSP values for \_SB.Pxxx */ |
| 358 | proc_blk_len = 6; |
| 359 | proc_blk_addr = ACPI_GPE0_BLK; |
| 360 | } else { |
| 361 | /* AP values for \_SB.Pxxx */ |
| 362 | proc_blk_addr = 0; |
| 363 | proc_blk_len = 0; |
| 364 | } |
| 365 | |
| 366 | acpigen_write_processor(cpu, proc_blk_addr, proc_blk_len); |
| 367 | |
| 368 | acpigen_write_pct_package(&perf_ctrl, &perf_sts); |
| 369 | |
| 370 | acpigen_write_pss_object(pstate_values, pstate_count); |
| 371 | |
| 372 | acpigen_write_xpss_object(pstate_xpss_values, pstate_count); |
| 373 | |
| 374 | if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) |
| 375 | acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, |
| 376 | HW_ALL); |
| 377 | else |
| 378 | acpigen_write_PSD_package(0, logical_cores, SW_ALL); |
| 379 | |
| 380 | acpigen_write_PPC(0); |
| 381 | |
| 382 | acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info)); |
| 383 | |
| 384 | acpigen_write_CSD_package(cpu >> 1, threads_per_core, HW_ALL, 0); |
| 385 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 386 | acpigen_pop_len(); |
| 387 | } |
| 388 | } |
| 389 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 390 | unsigned long southbridge_write_acpi_tables(const struct device *device, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 391 | unsigned long current, |
| 392 | struct acpi_rsdp *rsdp) |
| 393 | { |
| 394 | return acpi_write_hpet(device, current, rsdp); |
| 395 | } |
| 396 | |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 397 | void acpi_create_gnvs(struct global_nvs *gnvs) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 398 | { |
| 399 | /* Clear out GNVS. */ |
| 400 | memset(gnvs, 0, sizeof(*gnvs)); |
| 401 | |
| 402 | if (CONFIG(CONSOLE_CBMEM)) |
| 403 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 404 | |
| 405 | if (CONFIG(CHROMEOS)) { |
| 406 | /* Initialize Verified Boot data */ |
| 407 | chromeos_init_chromeos_acpi(&gnvs->chromeos); |
| 408 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 409 | } |
| 410 | |
| 411 | /* Set unknown wake source */ |
| 412 | gnvs->pm1i = ~0ULL; |
| 413 | gnvs->gpei = ~0ULL; |
| 414 | |
| 415 | /* CPU core count */ |
| 416 | gnvs->pcnt = dev_count_cpu(); |
| 417 | } |
| 418 | |
Furquan Shaikh | 338fd9a | 2020-04-24 22:57:05 -0700 | [diff] [blame] | 419 | void southbridge_inject_dsdt(const struct device *device) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 420 | { |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 421 | struct global_nvs *gnvs; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 422 | |
| 423 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 424 | |
| 425 | if (gnvs) { |
| 426 | acpi_create_gnvs(gnvs); |
| 427 | |
| 428 | /* Add it to DSDT */ |
| 429 | acpigen_write_scope("\\"); |
| 430 | acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); |
| 431 | acpigen_pop_len(); |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) |
| 436 | { |
| 437 | /* |
| 438 | * Store (\_SB.GPR2 (addr), Local5) |
| 439 | * \_SB.GPR2 is used to read control byte 2 from control register. |
| 440 | * / It is defined in gpio_lib.asl. |
| 441 | */ |
| 442 | acpigen_write_store(); |
| 443 | acpigen_emit_namestring("\\_SB.GPR2"); |
| 444 | acpigen_write_integer(addr); |
| 445 | acpigen_emit_byte(LOCAL5_OP); |
| 446 | } |
| 447 | |
| 448 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 449 | { |
| 450 | if (gpio_num >= SOC_GPIO_TOTAL_PINS) { |
| 451 | printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" |
| 452 | " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); |
| 453 | return -1; |
| 454 | } |
Kyösti Mälkki | 39bd46f | 2020-06-18 19:18:21 +0300 | [diff] [blame] | 455 | uintptr_t addr = gpio_get_address(gpio_num); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 456 | |
| 457 | acpigen_soc_get_gpio_in_local5(addr); |
| 458 | |
| 459 | /* If (And (Local5, mask)) */ |
| 460 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 461 | |
| 462 | /* Store (One, Local0) */ |
| 463 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 464 | |
| 465 | acpigen_pop_len(); /* If */ |
| 466 | |
| 467 | /* Else */ |
| 468 | acpigen_write_else(); |
| 469 | |
| 470 | /* Store (Zero, Local0) */ |
| 471 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 472 | |
| 473 | acpigen_pop_len(); /* Else */ |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
| 478 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 479 | { |
| 480 | if (gpio_num >= SOC_GPIO_TOTAL_PINS) { |
| 481 | printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" |
| 482 | " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); |
| 483 | return -1; |
| 484 | } |
Kyösti Mälkki | 39bd46f | 2020-06-18 19:18:21 +0300 | [diff] [blame] | 485 | uintptr_t addr = gpio_get_address(gpio_num); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 486 | |
| 487 | /* Store (0x40, Local0) */ |
| 488 | acpigen_write_store(); |
| 489 | acpigen_write_integer(GPIO_PIN_OUT); |
| 490 | acpigen_emit_byte(LOCAL0_OP); |
| 491 | |
| 492 | acpigen_soc_get_gpio_in_local5(addr); |
| 493 | |
| 494 | if (val) { |
| 495 | /* Or (Local5, GPIO_PIN_OUT, Local5) */ |
| 496 | acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); |
| 497 | } else { |
| 498 | /* Not (GPIO_PIN_OUT, Local6) */ |
| 499 | acpigen_write_not(LOCAL0_OP, LOCAL6_OP); |
| 500 | |
| 501 | /* And (Local5, Local6, Local5) */ |
| 502 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 503 | } |
| 504 | |
| 505 | /* |
| 506 | * SB.GPW2 (addr, Local5) |
| 507 | * \_SB.GPW2 is used to write control byte in control register |
| 508 | * / byte 2. It is defined in gpio_lib.asl. |
| 509 | */ |
| 510 | acpigen_emit_namestring("\\_SB.GPW2"); |
| 511 | acpigen_write_integer(addr); |
| 512 | acpigen_emit_byte(LOCAL5_OP); |
| 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | |
| 517 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 518 | { |
| 519 | return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); |
| 520 | } |
| 521 | |
| 522 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 523 | { |
| 524 | return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); |
| 525 | } |
| 526 | |
| 527 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 528 | { |
| 529 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 530 | } |
| 531 | |
| 532 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 533 | { |
| 534 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 535 | } |