Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 2 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 3 | #include <cbmem.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 4 | #include <console/console.h> |
Elyes HAOUAS | 748caed | 2019-12-19 17:02:08 +0100 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | #include <device/device.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 9 | #include <boot/tables.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 10 | #include <acpi/acpi.h> |
Angel Pons | 2a8ceef | 2020-09-15 12:23:45 +0200 | [diff] [blame] | 11 | #include <northbridge/intel/x4x/memmap.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 12 | #include <northbridge/intel/x4x/chip.h> |
| 13 | #include <northbridge/intel/x4x/x4x.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 14 | #include <cpu/intel/smm_reloc.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 15 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 16 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 17 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 18 | static void mch_domain_read_resources(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 19 | { |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 20 | u8 index; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 21 | u64 tom, touud; |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 22 | u32 tomk, tolud, delta_cbmem; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 23 | u32 uma_sizek = 0; |
| 24 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 25 | const u32 top32memk = 4 * (GiB / KiB); |
| 26 | index = 3; |
| 27 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 28 | pci_domain_read_resources(dev); |
| 29 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 30 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 31 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 32 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 33 | touud = pci_read_config16(mch, D0F0_TOUUD); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 34 | touud <<= 20; |
| 35 | |
| 36 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 37 | tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 38 | tolud <<= 16; |
| 39 | |
| 40 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 41 | tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 42 | tom <<= 26; |
| 43 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 44 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 45 | |
| 46 | tomk = tolud >> 10; |
| 47 | |
| 48 | /* Graphics memory comes next */ |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 49 | |
Arthur Heymans | c6e13b6 | 2018-06-26 21:06:38 +0200 | [diff] [blame] | 50 | const u16 ggc = pci_read_config16(mch, D0F0_GGC); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 51 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 52 | |
| 53 | /* Graphics memory */ |
| 54 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 55 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 56 | tomk -= gms_sizek; |
| 57 | uma_sizek += gms_sizek; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 58 | |
| 59 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 60 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 61 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 62 | tomk -= gsm_sizek; |
| 63 | uma_sizek += gsm_sizek; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 64 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 65 | printk(BIOS_DEBUG, "TSEG decoded, subtracting "); |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 66 | const u32 tseg_sizek = decode_tseg_size( |
| 67 | pci_read_config8(dev, D0F0_ESMRAMC)) >> 10; |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 68 | uma_sizek += tseg_sizek; |
| 69 | tomk -= tseg_sizek; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 70 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 71 | printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10); |
| 72 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 73 | /* cbmem_top can be shifted downwards due to alignment. |
| 74 | Mark the region between cbmem_top and tomk as unusable */ |
Arthur Heymans | 2aeb2a1 | 2021-07-02 10:05:09 +0200 | [diff] [blame^] | 75 | delta_cbmem = tomk - ((uint32_t)(uintptr_t)cbmem_top() >> 10); |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 76 | tomk -= delta_cbmem; |
| 77 | uma_sizek += delta_cbmem; |
| 78 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 79 | printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", delta_cbmem); |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 80 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 81 | printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 82 | |
| 83 | /* Report the memory regions */ |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 84 | ram_resource(dev, index++, 0, legacy_hole_base_k); |
| 85 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 86 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 87 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 88 | (0x100000 - 0xc0000) >> 10); |
| 89 | ram_resource(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10))); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 90 | |
| 91 | /* |
| 92 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 93 | * is remapped above TOM, TOUUD will account for both |
| 94 | */ |
| 95 | touud >>= 10; /* Convert to KB */ |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 96 | if (touud > top32memk) { |
| 97 | ram_resource(dev, index++, top32memk, touud - top32memk); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 98 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 99 | (touud - top32memk) >> 10); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 100 | } |
| 101 | |
Angel Pons | dd7ce4e | 2021-03-26 23:21:02 +0100 | [diff] [blame] | 102 | printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x size=0x%08x\n", |
| 103 | tomk << 10, uma_sizek << 10); |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 104 | uma_resource(dev, index++, tomk, uma_sizek); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 105 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 106 | /* Reserve high memory where the NB BARs are up to 4GiB */ |
| 107 | fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10, |
| 108 | top32memk - (DEFAULT_HECIBAR >> 10), |
| 109 | IORESOURCE_RESERVE); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 110 | |
Angel Pons | bbc80f4 | 2021-01-20 13:23:18 +0100 | [diff] [blame] | 111 | mmconf_resource(dev, index++); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 112 | } |
| 113 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 114 | static void mch_domain_set_resources(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 115 | { |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 116 | struct resource *res; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 117 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 118 | for (res = dev->resource_list; res; res = res->next) |
| 119 | report_resource_stored(dev, res, ""); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 120 | |
| 121 | assign_resources(dev->link_list); |
| 122 | } |
| 123 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 124 | static void mch_domain_init(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 125 | { |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 126 | /* Enable SERR */ |
Elyes HAOUAS | 5ac723e | 2020-04-29 09:09:12 +0200 | [diff] [blame] | 127 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 128 | } |
| 129 | |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 130 | static const char *northbridge_acpi_name(const struct device *dev) |
| 131 | { |
| 132 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 133 | return "PCI0"; |
| 134 | |
| 135 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 136 | return NULL; |
| 137 | |
| 138 | switch (dev->path.pci.devfn) { |
| 139 | case PCI_DEVFN(0, 0): |
| 140 | return "MCHC"; |
| 141 | } |
| 142 | |
| 143 | return NULL; |
| 144 | } |
| 145 | |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 146 | void northbridge_write_smram(u8 smram) |
| 147 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 148 | struct device *dev = pcidev_on_root(0, 0); |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 149 | |
| 150 | if (dev == NULL) |
| 151 | die("could not find pci 00:00.0!\n"); |
| 152 | |
| 153 | pci_write_config8(dev, D0F0_SMRAM, smram); |
| 154 | } |
| 155 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 156 | static struct device_operations pci_domain_ops = { |
| 157 | .read_resources = mch_domain_read_resources, |
| 158 | .set_resources = mch_domain_set_resources, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 159 | .init = mch_domain_init, |
| 160 | .scan_bus = pci_domain_scan_bus, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 161 | .write_acpi_tables = northbridge_write_acpi_tables, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 162 | .acpi_fill_ssdt = generate_cpu_entries, |
Arthur Heymans | a8a9f34 | 2017-12-24 08:11:13 +0100 | [diff] [blame] | 163 | .acpi_name = northbridge_acpi_name, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 164 | }; |
| 165 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 166 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 167 | .read_resources = noop_read_resources, |
| 168 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 169 | .init = mp_cpu_bus_init, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 170 | }; |
| 171 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 172 | static void enable_dev(struct device *dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 173 | { |
| 174 | /* Set the operations if it is a special bus type */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 175 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 176 | dev->ops = &pci_domain_ops; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 177 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 178 | dev->ops = &cpu_bus_ops; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 179 | } |
| 180 | |
Arthur Heymans | a854c9d | 2019-11-27 21:53:01 +0100 | [diff] [blame] | 181 | static void hide_pci_fn(const int dev_bit_base, const struct device *dev) |
| 182 | { |
| 183 | if (!dev || dev->enabled) |
| 184 | return; |
| 185 | const unsigned int fn = PCI_FUNC(dev->path.pci.devfn); |
| 186 | const struct device *const d0f0 = pcidev_on_root(0, 0); |
| 187 | pci_update_config32(d0f0, D0F0_DEVEN, ~(1 << (dev_bit_base + fn)), 0); |
| 188 | } |
| 189 | |
| 190 | static void hide_pci_dev(const int dev, int functions, const int dev_bit_base) |
| 191 | { |
| 192 | for (; functions >= 0; functions--) |
| 193 | hide_pci_fn(dev_bit_base, pcidev_on_root(dev, functions)); |
| 194 | } |
| 195 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 196 | static void x4x_init(void *const chip_info) |
| 197 | { |
Kyösti Mälkki | 98a9174 | 2018-05-21 21:29:16 +0300 | [diff] [blame] | 198 | struct device *const d0f0 = pcidev_on_root(0x0, 0); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 199 | |
| 200 | /* Hide internal functions based on devicetree info. */ |
Arthur Heymans | a854c9d | 2019-11-27 21:53:01 +0100 | [diff] [blame] | 201 | hide_pci_dev(6, 0, 13); /* PEG1: only on P45 */ |
| 202 | hide_pci_dev(3, 3, 6); /* ME */ |
| 203 | hide_pci_dev(2, 1, 3); /* IGD */ |
| 204 | hide_pci_dev(1, 0, 1); /* PEG0 */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 205 | |
| 206 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 207 | if (!(deven & (0xf << 6))) |
| 208 | pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); |
| 209 | } |
| 210 | |
| 211 | struct chip_operations northbridge_intel_x4x_ops = { |
| 212 | CHIP_NAME("Intel 4-Series Northbridge") |
| 213 | .enable_dev = enable_dev, |
| 214 | .init = x4x_init, |
| 215 | }; |