Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 4 | * Copyright 2017-2018 Intel Inc. |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 16 | #include <assert.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 17 | #include <commonlib/helpers.h> |
| 18 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 19 | #include <device/mmio.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 20 | #include <delay.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <device/pci_ops.h> |
| 24 | #include <intelblocks/cse.h> |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 25 | #include <soc/iomap.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 27 | #include <string.h> |
| 28 | #include <timer.h> |
| 29 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 30 | #define MAX_HECI_MESSAGE_RETRY_COUNT 5 |
| 31 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 32 | /* Wait up to 15 sec for HECI to get ready */ |
| 33 | #define HECI_DELAY_READY (15 * 1000) |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 34 | /* Wait up to 100 usec between circular buffer polls */ |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 35 | #define HECI_DELAY 100 |
| 36 | /* Wait up to 5 sec for CSE to chew something we sent */ |
| 37 | #define HECI_SEND_TIMEOUT (5 * 1000) |
| 38 | /* Wait up to 5 sec for CSE to blurp a reply */ |
| 39 | #define HECI_READ_TIMEOUT (5 * 1000) |
| 40 | |
| 41 | #define SLOT_SIZE sizeof(uint32_t) |
| 42 | |
| 43 | #define MMIO_CSE_CB_WW 0x00 |
| 44 | #define MMIO_HOST_CSR 0x04 |
| 45 | #define MMIO_CSE_CB_RW 0x08 |
| 46 | #define MMIO_CSE_CSR 0x0c |
| 47 | |
| 48 | #define CSR_IE (1 << 0) |
| 49 | #define CSR_IS (1 << 1) |
| 50 | #define CSR_IG (1 << 2) |
| 51 | #define CSR_READY (1 << 3) |
| 52 | #define CSR_RESET (1 << 4) |
| 53 | #define CSR_RP_START 8 |
| 54 | #define CSR_RP (((1 << 8) - 1) << CSR_RP_START) |
| 55 | #define CSR_WP_START 16 |
| 56 | #define CSR_WP (((1 << 8) - 1) << CSR_WP_START) |
| 57 | #define CSR_CBD_START 24 |
| 58 | #define CSR_CBD (((1 << 8) - 1) << CSR_CBD_START) |
| 59 | |
| 60 | #define MEI_HDR_IS_COMPLETE (1 << 31) |
| 61 | #define MEI_HDR_LENGTH_START 16 |
| 62 | #define MEI_HDR_LENGTH_SIZE 9 |
| 63 | #define MEI_HDR_LENGTH (((1 << MEI_HDR_LENGTH_SIZE) - 1) \ |
| 64 | << MEI_HDR_LENGTH_START) |
| 65 | #define MEI_HDR_HOST_ADDR_START 8 |
| 66 | #define MEI_HDR_HOST_ADDR (((1 << 8) - 1) << MEI_HDR_HOST_ADDR_START) |
| 67 | #define MEI_HDR_CSE_ADDR_START 0 |
| 68 | #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) |
| 69 | |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 70 | #define HECI_OP_MODE_SEC_OVERRIDE 5 |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 71 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 72 | /* Global Reset Command ID */ |
| 73 | #define MKHI_GLOBAL_RESET_REQ 0xb |
| 74 | #define MKHI_GROUP_ID_CBM 0 |
| 75 | |
| 76 | /* RST Origin */ |
| 77 | #define GR_ORIGIN_BIOS_POST 2 |
| 78 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 79 | #define MKHI_HMRFPO_GROUP_ID 5 |
| 80 | |
| 81 | /* HMRFPO Command Ids */ |
| 82 | #define MKHI_HMRFPO_ENABLE 1 |
| 83 | #define MKHI_HMRFPO_GET_STATUS 3 |
| 84 | |
| 85 | #define ME_HFS_CWS_NORMAL 5 |
| 86 | #define ME_HFS_MODE_NORMAL 0 |
| 87 | #define ME_HFS_TEMP_DISABLE 3 |
| 88 | |
Arthur Heymans | 3d6ccd0 | 2019-05-27 17:25:23 +0200 | [diff] [blame] | 89 | static struct cse_device { |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 90 | uintptr_t sec_bar; |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 91 | } cse; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 92 | |
| 93 | /* |
| 94 | * Initialize the device with provided temporary BAR. If BAR is 0 use a |
| 95 | * default. This is intended for pre-mem usage only where BARs haven't been |
| 96 | * assigned yet and devices are not enabled. |
| 97 | */ |
| 98 | void heci_init(uintptr_t tempbar) |
| 99 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 100 | #if defined(__SIMPLE_DEVICE__) |
| 101 | pci_devfn_t dev = PCH_DEV_CSE; |
| 102 | #else |
| 103 | struct device *dev = PCH_DEV_CSE; |
| 104 | #endif |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 105 | u8 pcireg; |
| 106 | |
| 107 | /* Assume it is already initialized, nothing else to do */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 108 | if (cse.sec_bar) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 109 | return; |
| 110 | |
| 111 | /* Use default pre-ram bar */ |
| 112 | if (!tempbar) |
| 113 | tempbar = HECI1_BASE_ADDRESS; |
| 114 | |
| 115 | /* Assign Resources to HECI1 */ |
| 116 | /* Clear BIT 1-2 of Command Register */ |
| 117 | pcireg = pci_read_config8(dev, PCI_COMMAND); |
| 118 | pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 119 | pci_write_config8(dev, PCI_COMMAND, pcireg); |
| 120 | |
| 121 | /* Program Temporary BAR for HECI1 */ |
| 122 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); |
| 123 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); |
| 124 | |
| 125 | /* Enable Bus Master and MMIO Space */ |
| 126 | pcireg = pci_read_config8(dev, PCI_COMMAND); |
| 127 | pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 128 | pci_write_config8(dev, PCI_COMMAND, pcireg); |
| 129 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 130 | cse.sec_bar = tempbar; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 131 | } |
| 132 | |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 133 | /* Get HECI BAR 0 from PCI configuration space */ |
| 134 | static uint32_t get_cse_bar(void) |
| 135 | { |
| 136 | uintptr_t bar; |
| 137 | |
| 138 | bar = pci_read_config32(PCH_DEV_CSE, PCI_BASE_ADDRESS_0); |
| 139 | assert(bar != 0); |
| 140 | /* |
| 141 | * Bits 31-12 are the base address as per EDS for SPI, |
| 142 | * Don't care about 0-11 bit |
| 143 | */ |
| 144 | return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 145 | } |
| 146 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 147 | static uint32_t read_bar(uint32_t offset) |
| 148 | { |
Patrick Georgi | 08c8cf9 | 2019-12-02 11:43:20 +0100 | [diff] [blame] | 149 | /* Load and cache BAR */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 150 | if (!cse.sec_bar) |
| 151 | cse.sec_bar = get_cse_bar(); |
| 152 | return read32((void *)(cse.sec_bar + offset)); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | static void write_bar(uint32_t offset, uint32_t val) |
| 156 | { |
Patrick Georgi | 08c8cf9 | 2019-12-02 11:43:20 +0100 | [diff] [blame] | 157 | /* Load and cache BAR */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 158 | if (!cse.sec_bar) |
| 159 | cse.sec_bar = get_cse_bar(); |
| 160 | return write32((void *)(cse.sec_bar + offset), val); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | static uint32_t read_cse_csr(void) |
| 164 | { |
| 165 | return read_bar(MMIO_CSE_CSR); |
| 166 | } |
| 167 | |
| 168 | static uint32_t read_host_csr(void) |
| 169 | { |
| 170 | return read_bar(MMIO_HOST_CSR); |
| 171 | } |
| 172 | |
| 173 | static void write_host_csr(uint32_t data) |
| 174 | { |
| 175 | write_bar(MMIO_HOST_CSR, data); |
| 176 | } |
| 177 | |
| 178 | static size_t filled_slots(uint32_t data) |
| 179 | { |
| 180 | uint8_t wp, rp; |
| 181 | rp = data >> CSR_RP_START; |
| 182 | wp = data >> CSR_WP_START; |
| 183 | return (uint8_t) (wp - rp); |
| 184 | } |
| 185 | |
| 186 | static size_t cse_filled_slots(void) |
| 187 | { |
| 188 | return filled_slots(read_cse_csr()); |
| 189 | } |
| 190 | |
| 191 | static size_t host_empty_slots(void) |
| 192 | { |
| 193 | uint32_t csr; |
| 194 | csr = read_host_csr(); |
| 195 | |
| 196 | return ((csr & CSR_CBD) >> CSR_CBD_START) - filled_slots(csr); |
| 197 | } |
| 198 | |
| 199 | static void clear_int(void) |
| 200 | { |
| 201 | uint32_t csr; |
| 202 | csr = read_host_csr(); |
| 203 | csr |= CSR_IS; |
| 204 | write_host_csr(csr); |
| 205 | } |
| 206 | |
| 207 | static uint32_t read_slot(void) |
| 208 | { |
| 209 | return read_bar(MMIO_CSE_CB_RW); |
| 210 | } |
| 211 | |
| 212 | static void write_slot(uint32_t val) |
| 213 | { |
| 214 | write_bar(MMIO_CSE_CB_WW, val); |
| 215 | } |
| 216 | |
| 217 | static int wait_write_slots(size_t cnt) |
| 218 | { |
| 219 | struct stopwatch sw; |
| 220 | |
| 221 | stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT); |
| 222 | while (host_empty_slots() < cnt) { |
| 223 | udelay(HECI_DELAY); |
| 224 | if (stopwatch_expired(&sw)) { |
| 225 | printk(BIOS_ERR, "HECI: timeout, buffer not drained\n"); |
| 226 | return 0; |
| 227 | } |
| 228 | } |
| 229 | return 1; |
| 230 | } |
| 231 | |
| 232 | static int wait_read_slots(size_t cnt) |
| 233 | { |
| 234 | struct stopwatch sw; |
| 235 | |
| 236 | stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); |
| 237 | while (cse_filled_slots() < cnt) { |
| 238 | udelay(HECI_DELAY); |
| 239 | if (stopwatch_expired(&sw)) { |
| 240 | printk(BIOS_ERR, "HECI: timed out reading answer!\n"); |
| 241 | return 0; |
| 242 | } |
| 243 | } |
| 244 | return 1; |
| 245 | } |
| 246 | |
| 247 | /* get number of full 4-byte slots */ |
| 248 | static size_t bytes_to_slots(size_t bytes) |
| 249 | { |
| 250 | return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; |
| 251 | } |
| 252 | |
| 253 | static int cse_ready(void) |
| 254 | { |
| 255 | uint32_t csr; |
| 256 | csr = read_cse_csr(); |
| 257 | return csr & CSR_READY; |
| 258 | } |
| 259 | |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 260 | /* |
| 261 | * Checks if CSE is in SEC_OVERRIDE operation mode. This is the mode where |
| 262 | * CSE will allow reflashing of CSE region. |
| 263 | */ |
| 264 | static uint8_t check_cse_sec_override_mode(void) |
| 265 | { |
| 266 | union me_hfsts1 hfs1; |
| 267 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 268 | if (hfs1.fields.operation_mode == HECI_OP_MODE_SEC_OVERRIDE) |
| 269 | return 1; |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | /* Makes the host ready to communicate with CSE */ |
| 274 | void set_host_ready(void) |
| 275 | { |
| 276 | uint32_t csr; |
| 277 | csr = read_host_csr(); |
| 278 | csr &= ~CSR_RESET; |
| 279 | csr |= (CSR_IG | CSR_READY); |
| 280 | write_host_csr(csr); |
| 281 | } |
| 282 | |
| 283 | /* Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds */ |
| 284 | uint8_t wait_cse_sec_override_mode(void) |
| 285 | { |
| 286 | struct stopwatch sw; |
| 287 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); |
| 288 | while (!check_cse_sec_override_mode()) { |
| 289 | udelay(HECI_DELAY); |
| 290 | if (stopwatch_expired(&sw)) |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | return 1; |
| 295 | } |
| 296 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 297 | static int wait_heci_ready(void) |
| 298 | { |
| 299 | struct stopwatch sw; |
| 300 | |
| 301 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); |
| 302 | while (!cse_ready()) { |
| 303 | udelay(HECI_DELAY); |
| 304 | if (stopwatch_expired(&sw)) |
| 305 | return 0; |
| 306 | } |
| 307 | |
| 308 | return 1; |
| 309 | } |
| 310 | |
| 311 | static void host_gen_interrupt(void) |
| 312 | { |
| 313 | uint32_t csr; |
| 314 | csr = read_host_csr(); |
| 315 | csr |= CSR_IG; |
| 316 | write_host_csr(csr); |
| 317 | } |
| 318 | |
| 319 | static size_t hdr_get_length(uint32_t hdr) |
| 320 | { |
| 321 | return (hdr & MEI_HDR_LENGTH) >> MEI_HDR_LENGTH_START; |
| 322 | } |
| 323 | |
| 324 | static int |
| 325 | send_one_message(uint32_t hdr, const void *buff) |
| 326 | { |
| 327 | size_t pend_len, pend_slots, remainder, i; |
| 328 | uint32_t tmp; |
| 329 | const uint32_t *p = buff; |
| 330 | |
| 331 | /* Get space for the header */ |
| 332 | if (!wait_write_slots(1)) |
| 333 | return 0; |
| 334 | |
| 335 | /* First, write header */ |
| 336 | write_slot(hdr); |
| 337 | |
| 338 | pend_len = hdr_get_length(hdr); |
| 339 | pend_slots = bytes_to_slots(pend_len); |
| 340 | |
| 341 | if (!wait_write_slots(pend_slots)) |
| 342 | return 0; |
| 343 | |
| 344 | /* Write the body in whole slots */ |
| 345 | i = 0; |
| 346 | while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) { |
| 347 | write_slot(*p++); |
| 348 | i += SLOT_SIZE; |
| 349 | } |
| 350 | |
| 351 | remainder = pend_len % SLOT_SIZE; |
| 352 | /* Pad to 4 bytes not touching caller's buffer */ |
| 353 | if (remainder) { |
| 354 | memcpy(&tmp, p, remainder); |
| 355 | write_slot(tmp); |
| 356 | } |
| 357 | |
| 358 | host_gen_interrupt(); |
| 359 | |
| 360 | /* Make sure nothing bad happened during transmission */ |
| 361 | if (!cse_ready()) |
| 362 | return 0; |
| 363 | |
| 364 | return pend_len; |
| 365 | } |
| 366 | |
| 367 | int |
| 368 | heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr) |
| 369 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 370 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 371 | uint32_t csr, hdr; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 372 | size_t sent, remaining, cb_size, max_length; |
| 373 | const uint8_t *p; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 374 | |
| 375 | if (!msg || !len) |
| 376 | return 0; |
| 377 | |
| 378 | clear_int(); |
| 379 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 380 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 381 | p = msg; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 382 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 383 | if (!wait_heci_ready()) { |
| 384 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 385 | continue; |
| 386 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 387 | |
Subrata Banik | 4a722f5 | 2017-11-13 14:56:42 +0530 | [diff] [blame] | 388 | csr = read_host_csr(); |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 389 | cb_size = ((csr & CSR_CBD) >> CSR_CBD_START) * SLOT_SIZE; |
| 390 | /* |
| 391 | * Reserve one slot for the header. Limit max message |
| 392 | * length by 9 bits that are available in the header. |
| 393 | */ |
| 394 | max_length = MIN(cb_size, (1 << MEI_HDR_LENGTH_SIZE) - 1) |
| 395 | - SLOT_SIZE; |
| 396 | remaining = len; |
| 397 | |
| 398 | /* |
| 399 | * Fragment the message into smaller messages not exceeding |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 400 | * useful circular buffer length. Mark last message complete. |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 401 | */ |
| 402 | do { |
| 403 | hdr = MIN(max_length, remaining) |
| 404 | << MEI_HDR_LENGTH_START; |
| 405 | hdr |= client_addr << MEI_HDR_CSE_ADDR_START; |
| 406 | hdr |= host_addr << MEI_HDR_HOST_ADDR_START; |
| 407 | hdr |= (MIN(max_length, remaining) == remaining) ? |
Lee Leahy | 68ab0b5 | 2017-03-10 13:42:34 -0800 | [diff] [blame] | 408 | MEI_HDR_IS_COMPLETE : 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 409 | sent = send_one_message(hdr, p); |
| 410 | p += sent; |
| 411 | remaining -= sent; |
| 412 | } while (remaining > 0 && sent != 0); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 413 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 414 | if (!remaining) |
| 415 | return 1; |
| 416 | } |
| 417 | return 0; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 418 | } |
| 419 | |
| 420 | static size_t |
| 421 | recv_one_message(uint32_t *hdr, void *buff, size_t maxlen) |
| 422 | { |
| 423 | uint32_t reg, *p = buff; |
| 424 | size_t recv_slots, recv_len, remainder, i; |
| 425 | |
| 426 | /* first get the header */ |
| 427 | if (!wait_read_slots(1)) |
| 428 | return 0; |
| 429 | |
| 430 | *hdr = read_slot(); |
| 431 | recv_len = hdr_get_length(*hdr); |
| 432 | |
| 433 | if (!recv_len) |
| 434 | printk(BIOS_WARNING, "HECI: message is zero-sized\n"); |
| 435 | |
| 436 | recv_slots = bytes_to_slots(recv_len); |
| 437 | |
| 438 | i = 0; |
| 439 | if (recv_len > maxlen) { |
| 440 | printk(BIOS_ERR, "HECI: response is too big\n"); |
| 441 | return 0; |
| 442 | } |
| 443 | |
| 444 | /* wait for the rest of messages to arrive */ |
| 445 | wait_read_slots(recv_slots); |
| 446 | |
| 447 | /* fetch whole slots first */ |
| 448 | while (i < ALIGN_DOWN(recv_len, SLOT_SIZE)) { |
| 449 | *p++ = read_slot(); |
| 450 | i += SLOT_SIZE; |
| 451 | } |
| 452 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 453 | /* |
| 454 | * If ME is not ready, something went wrong and |
| 455 | * we received junk |
| 456 | */ |
| 457 | if (!cse_ready()) |
| 458 | return 0; |
| 459 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 460 | remainder = recv_len % SLOT_SIZE; |
| 461 | |
| 462 | if (remainder) { |
| 463 | reg = read_slot(); |
| 464 | memcpy(p, ®, remainder); |
| 465 | } |
| 466 | |
| 467 | return recv_len; |
| 468 | } |
| 469 | |
| 470 | int heci_receive(void *buff, size_t *maxlen) |
| 471 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 472 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 473 | size_t left, received; |
| 474 | uint32_t hdr = 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 475 | uint8_t *p; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 476 | |
| 477 | if (!buff || !maxlen || !*maxlen) |
| 478 | return 0; |
| 479 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 480 | clear_int(); |
| 481 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 482 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 483 | p = buff; |
| 484 | left = *maxlen; |
| 485 | |
| 486 | if (!wait_heci_ready()) { |
| 487 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 488 | continue; |
| 489 | } |
| 490 | |
| 491 | /* |
| 492 | * Receive multiple packets until we meet one marked |
| 493 | * complete or we run out of space in caller-provided buffer. |
| 494 | */ |
| 495 | do { |
| 496 | received = recv_one_message(&hdr, p, left); |
Lijian Zhao | c50296d | 2017-12-15 19:10:18 -0800 | [diff] [blame] | 497 | if (!received) { |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame] | 498 | printk(BIOS_ERR, "HECI: Failed to receive!\n"); |
Lijian Zhao | c50296d | 2017-12-15 19:10:18 -0800 | [diff] [blame] | 499 | return 0; |
| 500 | } |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 501 | left -= received; |
| 502 | p += received; |
| 503 | /* If we read out everything ping to send more */ |
| 504 | if (!(hdr & MEI_HDR_IS_COMPLETE) && !cse_filled_slots()) |
| 505 | host_gen_interrupt(); |
| 506 | } while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0); |
| 507 | |
| 508 | if ((hdr & MEI_HDR_IS_COMPLETE) && received) { |
| 509 | *maxlen = p - (uint8_t *) buff; |
| 510 | return 1; |
| 511 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 512 | } |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 513 | return 0; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 514 | } |
| 515 | |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 516 | int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz) |
| 517 | { |
| 518 | if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, HECI_MKHI_ADDR)) { |
| 519 | printk(BIOS_ERR, "HECI: send Failed\n"); |
| 520 | return 0; |
| 521 | } |
| 522 | |
| 523 | if (rcv_msg != NULL) { |
| 524 | if (!heci_receive(rcv_msg, rcv_sz)) { |
| 525 | printk(BIOS_ERR, "HECI: receive Failed\n"); |
| 526 | return 0; |
| 527 | } |
| 528 | } |
| 529 | return 1; |
| 530 | } |
| 531 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 532 | /* |
| 533 | * Attempt to reset the device. This is useful when host and ME are out |
| 534 | * of sync during transmission or ME didn't understand the message. |
| 535 | */ |
| 536 | int heci_reset(void) |
| 537 | { |
| 538 | uint32_t csr; |
| 539 | |
| 540 | /* Send reset request */ |
| 541 | csr = read_host_csr(); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 542 | csr |= (CSR_RESET | CSR_IG); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 543 | write_host_csr(csr); |
| 544 | |
| 545 | if (wait_heci_ready()) { |
| 546 | /* Device is back on its imaginary feet, clear reset */ |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 547 | set_host_ready(); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 548 | return 1; |
| 549 | } |
| 550 | |
| 551 | printk(BIOS_CRIT, "HECI: reset failed\n"); |
| 552 | |
| 553 | return 0; |
| 554 | } |
| 555 | |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 556 | bool is_cse_enabled(void) |
| 557 | { |
| 558 | const struct device *cse_dev = pcidev_path_on_root(PCH_DEVFN_CSE); |
| 559 | |
| 560 | if (!cse_dev || !cse_dev->enabled) { |
| 561 | printk(BIOS_WARNING, "HECI: No CSE device\n"); |
| 562 | return false; |
| 563 | } |
| 564 | |
| 565 | if (pci_read_config16(PCH_DEV_CSE, PCI_VENDOR_ID) == 0xFFFF) { |
| 566 | printk(BIOS_WARNING, "HECI: CSE device is hidden\n"); |
| 567 | return false; |
| 568 | } |
| 569 | |
| 570 | return true; |
| 571 | } |
| 572 | |
| 573 | uint32_t me_read_config32(int offset) |
| 574 | { |
| 575 | return pci_read_config32(PCH_DEV_CSE, offset); |
| 576 | } |
| 577 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 578 | /* |
| 579 | * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/ |
| 580 | * HOST_RESET_ONLY/CSE_RESET_ONLY. |
| 581 | */ |
| 582 | int send_heci_reset_req_message(uint8_t rst_type) |
| 583 | { |
| 584 | int status; |
| 585 | struct mkhi_hdr reply; |
| 586 | struct reset_message { |
| 587 | struct mkhi_hdr hdr; |
| 588 | uint8_t req_origin; |
| 589 | uint8_t reset_type; |
| 590 | } __packed; |
| 591 | struct reset_message msg = { |
| 592 | .hdr = { |
| 593 | .group_id = MKHI_GROUP_ID_CBM, |
| 594 | .command = MKHI_GLOBAL_RESET_REQ, |
| 595 | }, |
| 596 | .req_origin = GR_ORIGIN_BIOS_POST, |
| 597 | .reset_type = rst_type |
| 598 | }; |
| 599 | size_t reply_size; |
| 600 | |
| 601 | if (!((rst_type == GLOBAL_RESET) || |
| 602 | (rst_type == HOST_RESET_ONLY) || (rst_type == CSE_RESET_ONLY))) |
| 603 | return -1; |
| 604 | |
| 605 | heci_reset(); |
| 606 | |
| 607 | reply_size = sizeof(reply); |
| 608 | memset(&reply, 0, reply_size); |
| 609 | |
| 610 | printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); |
| 611 | if (rst_type == CSE_RESET_ONLY) |
| 612 | status = heci_send_receive(&msg, sizeof(msg), NULL, 0); |
| 613 | else |
| 614 | status = heci_send_receive(&msg, sizeof(msg), &reply, |
| 615 | &reply_size); |
| 616 | |
| 617 | if (status != 1) |
| 618 | return -1; |
| 619 | |
| 620 | printk(BIOS_DEBUG, "HECI: Global Reset success!\n"); |
| 621 | return 0; |
| 622 | } |
| 623 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 624 | /* Sends HMRFPO Enable command to CSE */ |
| 625 | int send_hmrfpo_enable_msg(void) |
| 626 | { |
| 627 | struct hmrfpo_enable_msg { |
| 628 | struct mkhi_hdr hdr; |
| 629 | uint32_t nonce[2]; |
| 630 | } __packed; |
| 631 | |
| 632 | /* HMRFPO Enable message */ |
| 633 | struct hmrfpo_enable_msg msg = { |
| 634 | .hdr = { |
| 635 | .group_id = MKHI_HMRFPO_GROUP_ID, |
| 636 | .command = MKHI_HMRFPO_ENABLE, |
| 637 | }, |
| 638 | .nonce = {0}, |
| 639 | }; |
| 640 | |
| 641 | /* HMRFPO Enable response */ |
| 642 | struct hmrfpo_enable_resp { |
| 643 | struct mkhi_hdr hdr; |
| 644 | uint32_t fct_base; |
| 645 | uint32_t fct_limit; |
| 646 | uint8_t status; |
| 647 | uint8_t padding[3]; |
| 648 | } __packed; |
| 649 | |
| 650 | struct hmrfpo_enable_resp resp; |
| 651 | size_t resp_size = sizeof(struct hmrfpo_enable_resp); |
| 652 | union me_hfsts1 hfs1; |
| 653 | |
| 654 | printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); |
| 655 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 656 | /* |
| 657 | * This command can be run only if: |
| 658 | * - Working state is normal and |
| 659 | * - Operation mode is normal or temporary disable mode. |
| 660 | */ |
| 661 | if (hfs1.fields.working_state != ME_HFS_CWS_NORMAL || |
| 662 | (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL && |
| 663 | hfs1.fields.operation_mode != ME_HFS_TEMP_DISABLE)) { |
| 664 | printk(BIOS_ERR, "HECI: ME not in required Mode\n"); |
| 665 | goto failed; |
| 666 | } |
| 667 | |
| 668 | if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), |
| 669 | &resp, &resp_size)) |
| 670 | goto failed; |
| 671 | |
| 672 | if (resp.hdr.result) { |
| 673 | printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); |
| 674 | goto failed; |
| 675 | } |
| 676 | return 1; |
| 677 | |
| 678 | failed: |
| 679 | return 0; |
| 680 | } |
| 681 | |
| 682 | /* |
| 683 | * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. |
| 684 | * The status can be DISABLES/LOCKED/ENABLED |
| 685 | */ |
| 686 | int send_hmrfpo_get_status_msg(void) |
| 687 | { |
| 688 | struct hmrfpo_get_status_msg { |
| 689 | struct mkhi_hdr hdr; |
| 690 | } __packed; |
| 691 | |
| 692 | struct hmrfpo_get_status_resp { |
| 693 | struct mkhi_hdr hdr; |
| 694 | uint8_t status; |
| 695 | uint8_t padding[3]; |
| 696 | } __packed; |
| 697 | |
| 698 | struct hmrfpo_get_status_msg msg = { |
| 699 | .hdr = { |
| 700 | .group_id = MKHI_HMRFPO_GROUP_ID, |
| 701 | .command = MKHI_HMRFPO_GET_STATUS, |
| 702 | }, |
| 703 | }; |
| 704 | struct hmrfpo_get_status_resp resp; |
| 705 | size_t resp_size = sizeof(struct hmrfpo_get_status_resp); |
| 706 | |
| 707 | printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n"); |
| 708 | |
| 709 | if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), |
| 710 | &resp, &resp_size)) { |
| 711 | printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); |
| 712 | return -1; |
| 713 | } |
| 714 | |
| 715 | if (resp.hdr.result) { |
| 716 | printk(BIOS_ERR, "HECI: HMRFPO Resp Failed:%d\n", |
| 717 | resp.hdr.result); |
| 718 | return -1; |
| 719 | } |
| 720 | |
| 721 | return resp.status; |
| 722 | } |
| 723 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 724 | #if ENV_RAMSTAGE |
| 725 | |
| 726 | static void update_sec_bar(struct device *dev) |
| 727 | { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 728 | cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | static void cse_set_resources(struct device *dev) |
| 732 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 733 | if (dev->path.pci.devfn == PCH_DEVFN_CSE) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 734 | update_sec_bar(dev); |
| 735 | |
| 736 | pci_dev_set_resources(dev); |
| 737 | } |
| 738 | |
| 739 | static struct device_operations cse_ops = { |
| 740 | .set_resources = cse_set_resources, |
| 741 | .read_resources = pci_dev_read_resources, |
| 742 | .enable_resources = pci_dev_enable_resources, |
| 743 | .init = pci_dev_init, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 744 | .ops_pci = &pci_dev_ops_pci, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 745 | }; |
| 746 | |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 747 | static const unsigned short pci_device_ids[] = { |
| 748 | PCI_DEVICE_ID_INTEL_APL_CSE0, |
| 749 | PCI_DEVICE_ID_INTEL_GLK_CSE0, |
Andrey Petrov | 0405de9 | 2017-06-05 13:25:29 -0700 | [diff] [blame] | 750 | PCI_DEVICE_ID_INTEL_CNL_CSE0, |
Subrata Banik | d0586d2 | 2017-11-27 13:28:41 +0530 | [diff] [blame] | 751 | PCI_DEVICE_ID_INTEL_SKL_CSE0, |
Maxim Polyakov | 571d07d | 2019-08-22 13:11:32 +0300 | [diff] [blame] | 752 | PCI_DEVICE_ID_INTEL_LWB_CSE0, |
| 753 | PCI_DEVICE_ID_INTEL_LWB_CSE0_SUPER, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 754 | PCI_DEVICE_ID_INTEL_CNP_H_CSE0, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 755 | PCI_DEVICE_ID_INTEL_ICL_CSE0, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 756 | PCI_DEVICE_ID_INTEL_CMP_CSE0, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame] | 757 | PCI_DEVICE_ID_INTEL_TGL_CSE0, |
rkanabar | 263f129 | 2019-11-28 10:41:45 +0530 | [diff] [blame^] | 758 | PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0, |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 759 | 0, |
| 760 | }; |
| 761 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 762 | static const struct pci_driver cse_driver __pci_driver = { |
| 763 | .ops = &cse_ops, |
| 764 | .vendor = PCI_VENDOR_ID_INTEL, |
| 765 | /* SoC/chipset needs to provide PCI device ID */ |
Andrey Petrov | 0405de9 | 2017-06-05 13:25:29 -0700 | [diff] [blame] | 766 | .devices = pci_device_ids |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 767 | }; |
| 768 | |
| 769 | #endif |