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review.coreboot.org / coreboot / 1fc0edd9fe6b8072a87dce769789119e81af978b / . / src / soc / amd / common / block / smbus / sm.c
blob: c5c1ed8990edf2559dfe6fef81a4ab86e0904496 [file] [log] [blame]
Angel Ponsae593872020-04-04 18:50:57 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]2
Furquan Shaikh38206882020-04-28 21:04:54 -0700[diff] [blame]3#include <amdblocks/acpimmio_map.h>
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]4#include <device/device.h>
5#include <device/pci.h>
6#include <device/pci_ids.h>
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]7#include <device/smbus.h>
Aaron Durbin178d6442020-01-28 11:10:23 -0700[diff] [blame]8#include <device/smbus_host.h>
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]9#include <arch/ioapic.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600[diff] [blame]10#include <soc/southbridge.h>
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]11
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]12/*
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600[diff] [blame]13* The southbridge enables all USB controllers by default in SMBUS Control.
14* The southbridge enables SATA by default in SMBUS Control.
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]15*/
16
Elyes HAOUAS777ccd42018-05-22 10:52:05 +0200[diff] [blame]17static void sm_init(struct device *dev)
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]18{
19 setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
20}
21
Richard Spiegelb40e1932018-10-24 12:51:21 -0700[diff] [blame]22static u32 get_sm_mmio(struct device *dev)
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]23{
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]24 struct resource *res;
25 struct bus *pbus;
26
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]27 pbus = get_pbus_smbus(dev);
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]28 res = find_resource(pbus->dev, 0x90);
Richard Spiegelb40e1932018-10-24 12:51:21 -0700[diff] [blame]29 if (res->base == SMB_BASE_ADDR)
Marshall Dawson5de47712019-05-01 16:14:42 -0600[diff] [blame]30 return ACPIMMIO_SMBUS_BASE;
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]31
Marshall Dawson5de47712019-05-01 16:14:42 -0600[diff] [blame]32 return ACPIMMIO_ASF_BASE;
Richard Spiegelb40e1932018-10-24 12:51:21 -0700[diff] [blame]33}
34
35static int lsmbus_recv_byte(struct device *dev)
36{
37 u8 device;
38
39 device = dev->path.i2c.device;
40 return do_smbus_recv_byte(get_sm_mmio(dev), device);
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]41}
42
Elyes HAOUAS777ccd42018-05-22 10:52:05 +0200[diff] [blame]43static int lsmbus_send_byte(struct device *dev, u8 val)
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]44{
Richard Spiegelcd04e312017-11-08 14:58:30 -0700[diff] [blame]45 u8 device;
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]46
47 device = dev->path.i2c.device;
Richard Spiegelb40e1932018-10-24 12:51:21 -0700[diff] [blame]48 return do_smbus_send_byte(get_sm_mmio(dev), device, val);
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]49}
50
Elyes HAOUAS777ccd42018-05-22 10:52:05 +0200[diff] [blame]51static int lsmbus_read_byte(struct device *dev, u8 address)
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]52{
Richard Spiegelcd04e312017-11-08 14:58:30 -0700[diff] [blame]53 u8 device;
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]54
55 device = dev->path.i2c.device;
Richard Spiegelb40e1932018-10-24 12:51:21 -0700[diff] [blame]56 return do_smbus_read_byte(get_sm_mmio(dev), device, address);
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]57}
58
Elyes HAOUAS777ccd42018-05-22 10:52:05 +0200[diff] [blame]59static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]60{
Richard Spiegelcd04e312017-11-08 14:58:30 -0700[diff] [blame]61 u8 device;
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]62
63 device = dev->path.i2c.device;
Richard Spiegelb40e1932018-10-24 12:51:21 -0700[diff] [blame]64 return do_smbus_write_byte(get_sm_mmio(dev), device, address, val);
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]65}
66static struct smbus_bus_operations lops_smbus_bus = {
67 .recv_byte = lsmbus_recv_byte,
68 .send_byte = lsmbus_send_byte,
69 .read_byte = lsmbus_read_byte,
70 .write_byte = lsmbus_write_byte,
71};
72
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]73static struct device_operations smbus_ops = {
Nico Huber2f8ba692020-04-05 14:05:24 +0200[diff] [blame]74 .read_resources = noop_read_resources,
75 .set_resources = noop_set_resources,
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]76 .enable_resources = pci_dev_enable_resources,
77 .init = sm_init,
78 .scan_bus = scan_smbus,
Angel Pons1fc0edd2020-05-31 00:03:28 +0200[diff] [blame^]79 .ops_pci = &pci_dev_ops_pci,
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]80 .ops_smbus_bus = &lops_smbus_bus,
81};
82static const struct pci_driver smbus_driver __pci_driver = {
83 .ops = &smbus_ops,
84 .vendor = PCI_VENDOR_ID_AMD,
Martin Roth069ca662018-03-01 11:26:18 -0700[diff] [blame]85 .device = PCI_DEVICE_ID_AMD_CZ_SMBUS,
Marc Jones24484842017-05-04 21:17:45 -0600[diff] [blame]86};