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Angel Pons4b429832020-04-02 23:48:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Damien Zammit43a1f782015-08-19 15:16:59 +10002
Arthur Heymans17ad4592018-08-06 15:35:28 +02003#include <cbmem.h>
Damien Zammit43a1f782015-08-19 15:16:59 +10004#include <console/console.h>
Elyes HAOUAS748caed2019-12-19 17:02:08 +01005#include <device/pci_def.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02006#include <device/pci_ops.h>
Damien Zammit43a1f782015-08-19 15:16:59 +10007#include <stdint.h>
8#include <device/device.h>
Damien Zammit43a1f782015-08-19 15:16:59 +10009#include <boot/tables.h>
Furquan Shaikh76cedd22020-05-02 10:24:23 -070010#include <acpi/acpi.h>
Angel Pons2a8ceef2020-09-15 12:23:45 +020011#include <northbridge/intel/x4x/memmap.h>
Damien Zammit43a1f782015-08-19 15:16:59 +100012#include <northbridge/intel/x4x/chip.h>
13#include <northbridge/intel/x4x/x4x.h>
Kyösti Mälkkif091f4d2019-08-14 03:49:21 +030014#include <cpu/intel/smm_reloc.h>
Damien Zammit43a1f782015-08-19 15:16:59 +100015
Elyes HAOUASfea02e12018-02-08 14:59:03 +010016static void mch_domain_read_resources(struct device *dev)
Damien Zammit43a1f782015-08-19 15:16:59 +100017{
Arthur Heymans4c65bfc2018-04-10 13:34:24 +020018 u8 index;
Damien Zammit43a1f782015-08-19 15:16:59 +100019 u64 tom, touud;
Arthur Heymans4c65bfc2018-04-10 13:34:24 +020020 u32 tomk, tolud, delta_cbmem;
Damien Zammit43a1f782015-08-19 15:16:59 +100021 u32 uma_sizek = 0;
22
Damien Zammit9fb08f52016-01-22 18:56:23 +110023 const u32 top32memk = 4 * (GiB / KiB);
24 index = 3;
25
Damien Zammit43a1f782015-08-19 15:16:59 +100026 pci_domain_read_resources(dev);
27
Kyösti Mälkkic70eed12018-05-22 02:18:00 +030028 struct device *mch = pcidev_on_root(0, 0);
Arthur Heymansc6e13b62018-06-26 21:06:38 +020029
Damien Zammit43a1f782015-08-19 15:16:59 +100030 /* Top of Upper Usable DRAM, including remap */
Arthur Heymansc6e13b62018-06-26 21:06:38 +020031 touud = pci_read_config16(mch, D0F0_TOUUD);
Damien Zammit43a1f782015-08-19 15:16:59 +100032 touud <<= 20;
33
34 /* Top of Lower Usable DRAM */
Arthur Heymansc6e13b62018-06-26 21:06:38 +020035 tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0;
Damien Zammit43a1f782015-08-19 15:16:59 +100036 tolud <<= 16;
37
38 /* Top of Memory - does not account for any UMA */
Arthur Heymansc6e13b62018-06-26 21:06:38 +020039 tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff;
Damien Zammit43a1f782015-08-19 15:16:59 +100040 tom <<= 26;
41
Angel Ponsdd7ce4e2021-03-26 23:21:02 +010042 printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom);
Damien Zammit43a1f782015-08-19 15:16:59 +100043
44 tomk = tolud >> 10;
45
46 /* Graphics memory comes next */
Arthur Heymans4c4f56a2017-02-27 13:46:11 +010047
Arthur Heymansc6e13b62018-06-26 21:06:38 +020048 const u16 ggc = pci_read_config16(mch, D0F0_GGC);
Damien Zammit43a1f782015-08-19 15:16:59 +100049 printk(BIOS_DEBUG, "IGD decoded, subtracting ");
50
51 /* Graphics memory */
52 const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
53 printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
Arthur Heymans4c4f56a2017-02-27 13:46:11 +010054 tomk -= gms_sizek;
55 uma_sizek += gms_sizek;
Damien Zammit43a1f782015-08-19 15:16:59 +100056
57 /* GTT Graphics Stolen Memory Size (GGMS) */
58 const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
59 printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
Arthur Heymans4c4f56a2017-02-27 13:46:11 +010060 tomk -= gsm_sizek;
61 uma_sizek += gsm_sizek;
Damien Zammit43a1f782015-08-19 15:16:59 +100062
Arthur Heymans4c4f56a2017-02-27 13:46:11 +010063 printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
Arthur Heymans4c65bfc2018-04-10 13:34:24 +020064 const u32 tseg_sizek = decode_tseg_size(
65 pci_read_config8(dev, D0F0_ESMRAMC)) >> 10;
Arthur Heymans4c4f56a2017-02-27 13:46:11 +010066 uma_sizek += tseg_sizek;
67 tomk -= tseg_sizek;
Damien Zammit43a1f782015-08-19 15:16:59 +100068
Arthur Heymans4c4f56a2017-02-27 13:46:11 +010069 printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10);
70
Arthur Heymans17ad4592018-08-06 15:35:28 +020071 /* cbmem_top can be shifted downwards due to alignment.
72 Mark the region between cbmem_top and tomk as unusable */
Kyösti Mälkki4e4edf72022-05-26 19:03:55 +030073 delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10);
Arthur Heymans17ad4592018-08-06 15:35:28 +020074 tomk -= delta_cbmem;
75 uma_sizek += delta_cbmem;
76
Angel Ponsdd7ce4e2021-03-26 23:21:02 +010077 printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", delta_cbmem);
Arthur Heymans17ad4592018-08-06 15:35:28 +020078
Arthur Heymans4c4f56a2017-02-27 13:46:11 +010079 printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
Damien Zammit43a1f782015-08-19 15:16:59 +100080
81 /* Report the memory regions */
Kyösti Mälkki8ee11b32021-06-27 21:08:32 +030082 ram_from_to(dev, index++, 0, 0xa0000);
83 mmio_from_to(dev, index++, 0xa0000, 0xc0000);
84 reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
Kyösti Mälkki27d62992022-05-24 20:25:58 +030085 ram_resource_kb(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10)));
Damien Zammit43a1f782015-08-19 15:16:59 +100086
87 /*
88 * If >= 4GB installed then memory from TOLUD to 4GB
89 * is remapped above TOM, TOUUD will account for both
90 */
Kyösti Mälkki0a18d642021-06-28 21:43:31 +030091 upper_ram_end(dev, index++, touud);
Damien Zammit43a1f782015-08-19 15:16:59 +100092
Angel Ponsdd7ce4e2021-03-26 23:21:02 +010093 printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x size=0x%08x\n",
94 tomk << 10, uma_sizek << 10);
Kyösti Mälkki27d62992022-05-24 20:25:58 +030095 uma_resource_kb(dev, index++, tomk, uma_sizek);
Damien Zammit43a1f782015-08-19 15:16:59 +100096
Damien Zammit9fb08f52016-01-22 18:56:23 +110097 /* Reserve high memory where the NB BARs are up to 4GiB */
Kyösti Mälkki27d62992022-05-24 20:25:58 +030098 fixed_mem_resource_kb(dev, index++, DEFAULT_HECIBAR >> 10,
Damien Zammit9fb08f52016-01-22 18:56:23 +110099 top32memk - (DEFAULT_HECIBAR >> 10),
100 IORESOURCE_RESERVE);
Damien Zammit43a1f782015-08-19 15:16:59 +1000101
Angel Ponsbbc80f42021-01-20 13:23:18 +0100102 mmconf_resource(dev, index++);
Damien Zammit43a1f782015-08-19 15:16:59 +1000103}
104
Elyes HAOUASfea02e12018-02-08 14:59:03 +0100105static void mch_domain_set_resources(struct device *dev)
Damien Zammit43a1f782015-08-19 15:16:59 +1000106{
Damien Zammit9fb08f52016-01-22 18:56:23 +1100107 struct resource *res;
Damien Zammit43a1f782015-08-19 15:16:59 +1000108
Damien Zammit9fb08f52016-01-22 18:56:23 +1100109 for (res = dev->resource_list; res; res = res->next)
110 report_resource_stored(dev, res, "");
Damien Zammit43a1f782015-08-19 15:16:59 +1000111
112 assign_resources(dev->link_list);
113}
114
Elyes HAOUASfea02e12018-02-08 14:59:03 +0100115static void mch_domain_init(struct device *dev)
Damien Zammit43a1f782015-08-19 15:16:59 +1000116{
Damien Zammit43a1f782015-08-19 15:16:59 +1000117 /* Enable SERR */
Elyes HAOUAS5ac723e2020-04-29 09:09:12 +0200118 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
Damien Zammit43a1f782015-08-19 15:16:59 +1000119}
120
Arthur Heymansa8a9f342017-12-24 08:11:13 +0100121static const char *northbridge_acpi_name(const struct device *dev)
122{
123 if (dev->path.type == DEVICE_PATH_DOMAIN)
124 return "PCI0";
125
126 if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
127 return NULL;
128
129 switch (dev->path.pci.devfn) {
130 case PCI_DEVFN(0, 0):
131 return "MCHC";
132 }
133
134 return NULL;
135}
136
Arthur Heymans4c65bfc2018-04-10 13:34:24 +0200137void northbridge_write_smram(u8 smram)
138{
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300139 struct device *dev = pcidev_on_root(0, 0);
Arthur Heymans4c65bfc2018-04-10 13:34:24 +0200140
141 if (dev == NULL)
142 die("could not find pci 00:00.0!\n");
143
144 pci_write_config8(dev, D0F0_SMRAM, smram);
145}
146
Damien Zammit43a1f782015-08-19 15:16:59 +1000147static struct device_operations pci_domain_ops = {
148 .read_resources = mch_domain_read_resources,
149 .set_resources = mch_domain_set_resources,
Damien Zammit43a1f782015-08-19 15:16:59 +1000150 .init = mch_domain_init,
151 .scan_bus = pci_domain_scan_bus,
Damien Zammit43a1f782015-08-19 15:16:59 +1000152 .write_acpi_tables = northbridge_write_acpi_tables,
Nico Huber68680dd2020-03-31 17:34:52 +0200153 .acpi_fill_ssdt = generate_cpu_entries,
Arthur Heymansa8a9f342017-12-24 08:11:13 +0100154 .acpi_name = northbridge_acpi_name,
Damien Zammit43a1f782015-08-19 15:16:59 +1000155};
156
Damien Zammit43a1f782015-08-19 15:16:59 +1000157static struct device_operations cpu_bus_ops = {
Nico Huber2f8ba692020-04-05 14:05:24 +0200158 .read_resources = noop_read_resources,
159 .set_resources = noop_set_resources,
Kyösti Mälkkib3267e02019-08-13 16:44:04 +0300160 .init = mp_cpu_bus_init,
Damien Zammit43a1f782015-08-19 15:16:59 +1000161};
162
Elyes HAOUASfea02e12018-02-08 14:59:03 +0100163static void enable_dev(struct device *dev)
Damien Zammit43a1f782015-08-19 15:16:59 +1000164{
165 /* Set the operations if it is a special bus type */
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100166 if (dev->path.type == DEVICE_PATH_DOMAIN)
Damien Zammit43a1f782015-08-19 15:16:59 +1000167 dev->ops = &pci_domain_ops;
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100168 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
Damien Zammit43a1f782015-08-19 15:16:59 +1000169 dev->ops = &cpu_bus_ops;
Damien Zammit43a1f782015-08-19 15:16:59 +1000170}
171
Arthur Heymansa854c9d2019-11-27 21:53:01 +0100172static void hide_pci_fn(const int dev_bit_base, const struct device *dev)
173{
174 if (!dev || dev->enabled)
175 return;
176 const unsigned int fn = PCI_FUNC(dev->path.pci.devfn);
177 const struct device *const d0f0 = pcidev_on_root(0, 0);
178 pci_update_config32(d0f0, D0F0_DEVEN, ~(1 << (dev_bit_base + fn)), 0);
179}
180
181static void hide_pci_dev(const int dev, int functions, const int dev_bit_base)
182{
183 for (; functions >= 0; functions--)
184 hide_pci_fn(dev_bit_base, pcidev_on_root(dev, functions));
185}
186
Damien Zammit43a1f782015-08-19 15:16:59 +1000187static void x4x_init(void *const chip_info)
188{
Kyösti Mälkki98a91742018-05-21 21:29:16 +0300189 struct device *const d0f0 = pcidev_on_root(0x0, 0);
Damien Zammit43a1f782015-08-19 15:16:59 +1000190
191 /* Hide internal functions based on devicetree info. */
Arthur Heymansa854c9d2019-11-27 21:53:01 +0100192 hide_pci_dev(6, 0, 13); /* PEG1: only on P45 */
193 hide_pci_dev(3, 3, 6); /* ME */
194 hide_pci_dev(2, 1, 3); /* IGD */
195 hide_pci_dev(1, 0, 1); /* PEG0 */
Damien Zammit43a1f782015-08-19 15:16:59 +1000196
197 const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
198 if (!(deven & (0xf << 6)))
199 pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14));
200}
201
202struct chip_operations northbridge_intel_x4x_ops = {
203 CHIP_NAME("Intel 4-Series Northbridge")
204 .enable_dev = enable_dev,
205 .init = x4x_init,
206};