src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
index de3d39e..426a542 100644
--- a/src/arch/x86/acpigen.c
+++ b/src/arch/x86/acpigen.c
@@ -453,7 +453,7 @@
* FIELDLIST_OFFSET(0x84),
* FIELDLIST_NAMESTR("PMCS", 2),
* };
- * acpigen_write_field("UART", l ,ARRAY_SIZE(l), FIELD_ANYACC | FIELD_NOLOCK |
+ * acpigen_write_field("UART", l, ARRAY_SIZE(l), FIELD_ANYACC | FIELD_NOLOCK |
* FIELD_PRESERVE);
* Output:
* Field (UART, AnyAcc, NoLock, Preserve)
diff --git a/src/commonlib/storage/storage_write.c b/src/commonlib/storage/storage_write.c
index ba60b41..aef8624 100644
--- a/src/commonlib/storage/storage_write.c
+++ b/src/commonlib/storage/storage_write.c
@@ -130,7 +130,7 @@
uint32_t *buffer = malloc(buffer_bytes);
uint32_t *ptr = buffer;
- for ( ; buffer_words ; buffer_words--)
+ for (; buffer_words ; buffer_words--)
*ptr++ = fill_pattern;
uint64_t todo = count;
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index 91b9ad7..428924d 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -682,7 +682,7 @@
do { // should we just go on instead ?
pstate_msr = rdmsr(PS_STS_REG);
- } while ( pstate_msr.lo != target_pstate );
+ } while (pstate_msr.lo != target_pstate);
}
}
diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
index 61da88c..d228858 100644
--- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
@@ -226,7 +226,7 @@
fam10h_rev_e = 1;
/*
- * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
+ * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit.
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1
* cmp_cap : 0x0 SingleCore; 0x1 DualCore; 0x2 TripleCore; 0x3 QuadCore; 0x4 QuintupleCore; 0x5 HexCore
*/
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 541d5a8..68b6953 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -129,7 +129,7 @@
msr = rdmsr(0x8b);
new_patch_id = msr.lo;
- UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id ,
+ UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id,
(new_patch_id == m->patch_id) ? "success" : "fail");
}
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
index 985a3c7..cbd80ce 100644
--- a/src/cpu/via/nano/nano_init.c
+++ b/src/cpu/via/nano/nano_init.c
@@ -71,7 +71,7 @@
printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n",
cur_vid, min_vid, max_vid);
- if ( (cur_fid != max_fid) || (cur_vid != max_vid) ) {
+ if ((cur_fid != max_fid) || (cur_vid != max_vid)) {
/* Set highest frequency and VID */
msr.lo = msr.hi;
msr.hi = 0;
@@ -101,7 +101,7 @@
* This MSR is not documented by VIA docs, other than setting these
* bits */
msr = rdmsr(NANO_MYSTERIOUS_MSR);
- msr.lo |= ( (1 << 7) | (1 << 4) );
+ msr.lo |= ((1 << 7) | (1 << 4));
/* FIXME: Do we have a 6-bit or 7-bit VRM?
* set bit [5] for 7-bit, or don't set it for 6 bit VRM
* This will probably require a Kconfig option
@@ -114,15 +114,15 @@
/* Enable TM3 */
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= ( (1 << 3) | (1 << 13) );
+ msr.lo |= ((1 << 3) | (1 << 13));
wrmsr(IA32_MISC_ENABLE, msr);
- u8 stepping = ( cpuid_eax(0x1) ) &0xf;
+ u8 stepping = (cpuid_eax(0x1)) & 0xf;
if (stepping >= MODEL_NANO_3000_B0) {
/* Hello Nano 3000. The Terminator needs a CPU upgrade */
/* Enable C1e, C2e, C3e, and C4e states */
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
+ msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
msr.hi |= (1 << 0); /* C4e */
wrmsr(IA32_MISC_ENABLE, msr);
}
diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c
index b8bfd7d..efabac6 100644
--- a/src/cpu/via/nano/update_ucode.c
+++ b/src/cpu/via/nano/update_ucode.c
@@ -43,9 +43,9 @@
static void nano_print_ucode_info(const nano_ucode_header *ucode)
{
printk(BIOS_SPEW, "Microcode update information:\n");
- printk(BIOS_SPEW, "Name: %8s\n", ucode->name );
+ printk(BIOS_SPEW, "Name: %8s\n", ucode->name);
printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month,
- ucode->day, ucode->year );
+ ucode->day, ucode->year);
}
static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
@@ -54,7 +54,7 @@
if (ucode->signature != NANO_UCODE_SIGNATURE)
return NANO_UCODE_SIGNATURE_ERROR;
/* The size of the head must be exactly 12 double words */
- if ( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
+ if ((ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
return NANO_UCODE_WRONG_SIZE;
/* How about a checksum ? Checksum must be 0
@@ -119,7 +119,7 @@
/* We might do a lot of loops searching for the microcode updates, but
* keep in mind, nano_ucode_is_valid searches for the signature before
* doing anything else. */
- for ( i = 0; i < (ucode_len >> 2); /* don't increment i here */ )
+ for (i = 0; i < (ucode_len >> 2); /* don't increment i here */)
{
ucode_update_status stat;
const nano_ucode_header * ucode = (void *)(&ucode_data[i]);
diff --git a/src/device/device.c b/src/device/device.c
index dcbaef1..7836af1 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -123,7 +123,7 @@
struct device *dev, *child;
/* Find the last child of our parent. */
- for (child = parent->children; child && child->sibling; /* */ )
+ for (child = parent->children; child && child->sibling; /* */)
child = child->sibling;
dev = malloc(sizeof(*dev));
diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c
index 66ff9d2..4a4609d 100644
--- a/src/device/hypertransport.c
+++ b/src/device/hypertransport.c
@@ -61,7 +61,7 @@
/* Now add the device to the list of devices on the bus. */
/* Find the last child of our parent. */
- for (child = first->bus->children; child && child->sibling; )
+ for (child = first->bus->children; child && child->sibling;)
child = child->sibling;
/* Place the chain on the list of children of their parent. */
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 8cd39e4..44b5100 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -275,7 +275,7 @@
pci_update_config32(root, root_cap + 0x08, ~0xff00,
(comm_mode_rst_time << 8));
- pci_update_config32(root, root_cap + 0x0c , 0xffffff04,
+ pci_update_config32(root, root_cap + 0x0c, 0xffffff04,
(endp_power_on_value << 3) | (power_on_scale));
/* TODO: 0xa0, 2 are values that work on some chipsets but really
@@ -291,7 +291,7 @@
L1SubStateSupport);
for (dev_t = dev; dev_t; dev_t = dev_t->sibling) {
- pci_update_config32(dev_t, end_cap + 0x0c , 0xffffff04,
+ pci_update_config32(dev_t, end_cap + 0x0c, 0xffffff04,
(endp_power_on_value << 3) | (power_on_scale));
pci_update_config32(dev_t, end_cap + 0x08,
diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c
index 3fcbb7c..cdd2c20 100644
--- a/src/drivers/emulation/qemu/bochs.c
+++ b/src/drivers/emulation/qemu/bochs.c
@@ -99,7 +99,7 @@
return;
printk(BIOS_DEBUG, "QEMU VGA: bochs dispi interface found, "
- "%d MiB video memory\n", mem / ( 1024 * 1024));
+ "%d MiB video memory\n", mem / (1024 * 1024));
printk(BIOS_DEBUG, "QEMU VGA: framebuffer @ %x (pci bar %d)\n",
addr, bar);
diff --git a/src/drivers/intel/fsp1_0/hob.c b/src/drivers/intel/fsp1_0/hob.c
index 9334893..9cf6f60 100644
--- a/src/drivers/intel/fsp1_0/hob.c
+++ b/src/drivers/intel/fsp1_0/hob.c
@@ -33,7 +33,7 @@
guid->Data4[0], guid->Data4[1],
guid->Data4[2], guid->Data4[3],
guid->Data4[4], guid->Data4[5],
- guid->Data4[6], guid->Data4[7] );
+ guid->Data4[6], guid->Data4[7]);
}
void print_hob_mem_attributes(void *Hobptr)
diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c
index ee44250..4070a1f 100644
--- a/src/drivers/intel/fsp2_0/hand_off_block.c
+++ b/src/drivers/intel/fsp2_0/hand_off_block.c
@@ -139,7 +139,7 @@
{
const struct hob_resource *res;
- for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;
+ for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
hob = fsp_next_hob(hob)) {
if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
@@ -202,7 +202,7 @@
if (!hob)
return NULL;
- for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;
+ for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
hob = fsp_next_hob(hob)) {
if (hob->type != HOB_TYPE_GUID_EXTENSION)
@@ -281,7 +281,7 @@
if (!hob)
return;
- for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;
+ for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
hob = fsp_next_hob(hob)) {
if (hob->type != HOB_TYPE_GUID_EXTENSION)
continue;
diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c
index 24a340f..10c2f12 100644
--- a/src/drivers/intel/fsp2_0/hob_display.c
+++ b/src/drivers/intel/fsp2_0/hob_display.c
@@ -116,7 +116,7 @@
{
const struct hob_header *hob = fsp_get_hob_list();
- for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;
+ for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
hob = fsp_next_hob(hob)) {
if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR)
fsp_print_resource_descriptor(hob);
diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c
index 13b301f..74bb6c6 100644
--- a/src/drivers/intel/gma/edid.c
+++ b/src/drivers/intel/gma/edid.c
@@ -46,15 +46,15 @@
wait_rdy(mmio);
write32(GMBUS5_ADDR, 0);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
- | GMBUS_CYCLE_STOP | ( 0x4 << GMBUS_BYTE_COUNT_SHIFT )
- | GMBUS_SLAVE_READ | (AT24_ADDR << 1) );
+ | GMBUS_CYCLE_STOP | (0x4 << GMBUS_BYTE_COUNT_SHIFT)
+ | GMBUS_SLAVE_READ | (AT24_ADDR << 1));
wait_rdy(mmio);
write32(GMBUS5_ADDR, 0);
write32(GMBUS1_ADDR, GMBUS_SW_CLR_INT);
write32(GMBUS1_ADDR, 0);
wait_rdy(mmio);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE
- | (AT24_ADDR << 1) );
+ | (AT24_ADDR << 1));
wait_rdy(mmio);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);
write32(GMBUS2_ADDR, GMBUS_INUSE);
@@ -80,13 +80,13 @@
/* Ensure index bits are disabled. */
write32(GMBUS5_ADDR, 0);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
- | (slave << 1) );
+ | (slave << 1));
wait_rdy(mmio);
/* Ensure index bits are disabled. */
write32(GMBUS5_ADDR, 0);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT
| GMBUS_CYCLE_STOP
- | (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
+ | (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1));
for (i = 0; i < edid_size / 4; i++) {
u32 reg32;
wait_rdy(mmio);
@@ -99,9 +99,9 @@
wait_rdy(mmio);
write32(GMBUS1_ADDR, GMBUS_SW_RDY
| GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP
- | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
+ | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1));
wait_rdy(mmio);
- write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP );
+ write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);
write32(GMBUS2_ADDR, GMBUS_INUSE);
printk (BIOS_SPEW, "EDID:\n");
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c
index 97c97a2..e197114 100644
--- a/src/drivers/intel/wifi/wifi.c
+++ b/src/drivers/intel/wifi/wifi.c
@@ -173,7 +173,7 @@
acpigen_write_package(2);
acpigen_write_dword(wgds->version);
/* Emit 'Domain Type' +
- * Group specific delta of power ( 6 bytes * NUM_WGDS_SAR_GROUPS )
+ * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS)
*/
package_size = sizeof(sar_limits.wgds.group) + 1;
acpigen_write_package(package_size);
diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c
index 75f3357..e02a331 100644
--- a/src/drivers/net/ne2k.c
+++ b/src/drivers/net/ne2k.c
@@ -287,7 +287,7 @@
if (dev == PCI_DEV_INVALID)
return 0;
- pci_write_config32(dev, 0x10, eth_nic_base | 1 );
+ pci_write_config32(dev, 0x10, eth_nic_base | 1);
pci_write_config8(dev, 0x4, 0x1);
c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET);
diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
index 8c01ac3..6b84614 100644
--- a/src/drivers/pc80/tpm/tis.c
+++ b/src/drivers/pc80/tpm/tis.c
@@ -46,7 +46,7 @@
#define TPM_DEBUG(fmt, args...) \
if (IS_ENABLED(CONFIG_DEBUG_TPM)) { \
printk(BIOS_DEBUG, PREFIX); \
- printk(BIOS_DEBUG, fmt , ##args); \
+ printk(BIOS_DEBUG, fmt, ##args); \
}
#define TPM_DEBUG_IO_READ(reg_, val_) \
TPM_DEBUG("Read reg 0x%x returns 0x%x\n", (reg_), (val_))
diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c
index 67d38ee..4463bad 100644
--- a/src/drivers/smmstore/store.c
+++ b/src/drivers/smmstore/store.c
@@ -29,7 +29,7 @@
* uint8_t value[value_sz]
* uint8_t active
* align to 4 bytes
- * )*
+ * )*
* uint32le_t endmarker = 0xffffffff
*
* active needs to be set to 0x00 for the entry to be valid. This satisfies
diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c
index aea6872..2626ec5 100644
--- a/src/drivers/spi/flashconsole.c
+++ b/src/drivers/spi/flashconsole.c
@@ -55,7 +55,7 @@
* the sector is already erased, so we would need to read
* anyways to check if it's all 0xff).
*/
- for (i = 0; i < len && offset < size; ) {
+ for (i = 0; i < len && offset < size;) {
// Fill the buffer on first iteration
if (i == 0) {
len = min(READ_BUFFER_SIZE, size - offset);
diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c
index 9ea8e79..e80bc35 100644
--- a/src/drivers/xgi/common/vb_setmode.c
+++ b/src/drivers/xgi/common/vb_setmode.c
@@ -2799,7 +2799,7 @@
static void XGI_SetCRT2FIFO(struct vb_device_info *pVBInfo)
{
- /* threshold high ,disable auto threshold */
+ /* threshold high, disable auto threshold */
xgifb_reg_set(pVBInfo->Part1Port, 0x01, 0x3B);
/* threshold low default 04h */
xgifb_reg_and_or(pVBInfo->Part1Port, 0x02, ~(0x3F), 0x04);
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 37939eb..fbd8ef6 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -155,7 +155,7 @@
printk(BIOS_SPEW, " (broken)\n");
} else {
printk(BIOS_SPEW,
- " %dx%d @ ( %s%s%s%s%s) Hz (%s%s preferred)\n",
+ " %dx%d @ (%s%s%s%s%s) Hz (%s%s preferred)\n",
width, height,
fifty ? "50 " : "",
sixty ? "60 " : "",
diff --git a/src/lib/stack.c b/src/lib/stack.c
index a66b6a1..ef45e2a 100644
--- a/src/lib/stack.c
+++ b/src/lib/stack.c
@@ -1,5 +1,5 @@
/*
-This software and ancillary information (herein called SOFTWARE )
+This software and ancillary information (herein called SOFTWARE)
called LinuxBIOS is made available under the terms described
here. The SOFTWARE has been approved for release with associated
LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
index 612ab5b..a273741 100644
--- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
+++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
@@ -142,7 +142,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c
index 98b59e7..da6d9ac 100644
--- a/src/mainboard/amd/lamar/BiosCallOuts.c
+++ b/src/mainboard/amd/lamar/BiosCallOuts.c
@@ -159,7 +159,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c
index 0ff1e9a..6f8baa9 100644
--- a/src/mainboard/amd/olivehill/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehill/BiosCallOuts.c
@@ -111,7 +111,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
index 92ba287..c5e51cd 100644
--- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
@@ -125,7 +125,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c
index b912d28..a900859 100644
--- a/src/mainboard/amd/parmer/BiosCallOuts.c
+++ b/src/mainboard/amd/parmer/BiosCallOuts.c
@@ -111,7 +111,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
index e355aae..9f273a4 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
@@ -49,7 +49,7 @@
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
- res->base, gsi_base );
+ res->base, gsi_base);
gsi_base+=7;
}
}
@@ -58,7 +58,7 @@
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
- res->base, gsi_base );
+ res->base, gsi_base);
gsi_base+=7;
}
}
@@ -66,9 +66,10 @@
int i;
int j = 0;
- for(i = 1; i < sysconf.hc_possible_num; i++) {
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
u32 d = 0;
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ if (!(sysconf.pci1234[i] & 0x1))
+ continue;
/* 8131 need to use +4 */
switch (sysconf.hcid[i]) {
case 1:
@@ -86,7 +87,7 @@
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
- res->base, gsi_base );
+ res->base, gsi_base);
gsi_base+=d;
}
}
@@ -95,7 +96,7 @@
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
- res->base, gsi_base );
+ res->base, gsi_base);
gsi_base+=d;
}
}
@@ -105,7 +106,7 @@
}
}
- current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 );
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
@@ -135,11 +136,12 @@
* change HCIN, and recalculate the checknum and add_table
*/
- for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
+ for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
const char *file_name;
- if((sysconf.pci1234[i] & 1) != 1 ) continue;
+ if ((sysconf.pci1234[i] & 1) != 1)
+ continue;
u8 c;
- if(i < 7) {
+ if (i < 7) {
c = (u8) ('4' + i - 1);
}
else {
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index 97a06ab..adf43c0 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -95,7 +95,7 @@
int i, j;
struct mb_sysconf_t *m;
- if(get_bus_conf_done == 1)
+ if (get_bus_conf_done == 1)
return; /* do it only once */
get_bus_conf_done = 1;
@@ -105,7 +105,7 @@
m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i = 0; i < sysconf.hc_possible_num; i++) {
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
@@ -144,8 +144,9 @@
/* HT chain 1 */
j = 0;
- for(i = 1; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
+ if (!(sysconf.pci1234[i] & 0x1))
+ continue;
/* check hcid type here */
sysconf.hcid[i] = get_hcid(i);
@@ -201,7 +202,7 @@
m->apicid_8111 = apicid_base + 0;
m->apicid_8132_1 = apicid_base + 1;
m->apicid_8132_2 = apicid_base + 2;
- for(i = 0; i < j; i++) {
+ for (i = 0; i < j; i++) {
m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
}
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index 0927199..3bc81e9 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -67,8 +67,9 @@
j = 0;
- for(i = 1; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
+ if (!(sysconf.pci1234[i] & 0x1))
+ continue;
switch(sysconf.hcid[i]) {
case 1:
@@ -106,32 +107,33 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
/* Slot 3 PCI 32 */
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
}
/* Slot 4 PCI 32 */
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
}
/* Slot 1 PCI-X 133/100/66 */
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4);
}
/* Slot 2 PCI-X 133/100/66 */
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */
}
j = 0;
- for(i = 1; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
+ if (!(sysconf.pci1234[i] & 0x1))
+ continue;
int ii;
int jj;
struct device *dev;
@@ -143,9 +145,9 @@
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- for(jj = 0; jj < 4; jj++) {
+ for (jj = 0; jj < 4; jj++) {
/* Slot 1 PCI-X 133/100/66 */
- for(ii = 0; ii < 4; ii++) {
+ for (ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4);
}
}
@@ -156,9 +158,9 @@
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- for(jj = 0; jj < 4; jj++) {
+ for (jj = 0; jj < 4; jj++) {
/* Slot 2 PCI-X 133/100/66 */
- for(ii = 0; ii < 4; ii++) {
+ for (ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */
}
}
diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c
index 9ebcdb2..2cbfbdf 100644
--- a/src/mainboard/amd/thatcher/BiosCallOuts.c
+++ b/src/mainboard/amd/thatcher/BiosCallOuts.c
@@ -111,7 +111,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index d4baf85..543b775 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -149,7 +149,7 @@
dword &= ~(1 << 10);
/* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
+ /* 1: enable two x8, 0: master slot enable only */
dword |= (1 << 26);
pci_write_config32(sm_dev, 0xfc, dword);
@@ -161,7 +161,7 @@
dword &= ~(1 << 10);
/* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
+ /* 1: enable two x8, 0: master slot enable only */
dword &= ~(1 << 26);
pci_write_config32(sm_dev, 0xfc, dword);
}
@@ -187,7 +187,7 @@
byte = ADT7461_read_byte(0x02); /* read status register to clear it */
ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+ printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte);
/* sb700 settings for thermal config */
/* set SB700 GPIO 64 to GPIO with pull-up */
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
index 7633cf3..4a8861c 100644
--- a/src/mainboard/amd/torpedo/gpio.c
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -91,7 +91,7 @@
Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
}
if (Index == GPIO_65) {
- if ( BoardType == 0 ) {
+ if (BoardType == 0) {
Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3
}
}
diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c
index 6b25d38..f70b88d 100644
--- a/src/mainboard/asus/am1i-a/BiosCallOuts.c
+++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c
@@ -125,7 +125,7 @@
/* Read SATA controller mode from CMOS */
enum cb_err ret;
ret = get_option(&FchParams_env->Sata.SataClass, "sata_mode");
- if ( ret != CB_SUCCESS) {
+ if (ret != CB_SUCCESS) {
FchParams_env->Sata.SataClass = 0;
printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret);
}
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index 00a12cc..0a0eedd 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -133,7 +133,7 @@
byte = ADT7461_read_byte(0x02); /* read status register to clear it */
ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+ printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte);
/* sb700 settings for thermal config */
/* set SB700 GPIO 64 to GPIO with pull-up */
@@ -172,7 +172,7 @@
* pm_iowrite(0x55, byte);
*
* byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
+ * byte &= ~(1 << 6);
* pm_iowrite(0x67, byte);
*/
}
diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
index 7723341..ef7cea8 100644
--- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
@@ -114,7 +114,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
index 7dc7ac6..63eb975 100644
--- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
@@ -127,7 +127,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
index 7698b4b..be6b5f5 100644
--- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
+++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
@@ -111,7 +111,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index 7caa4dc..2051884 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -59,37 +59,37 @@
static void ite_evc_conf(pnp_devfn_t dev)
{
ite_enter_conf(dev);
- it_sio_write(dev, 0xf1 , 0x40 );
- it_sio_write(dev, 0xf4 , 0x80 );
- it_sio_write(dev, 0xf5 , 0x00 );
- it_sio_write(dev, 0xf6 , 0xf0 );
- it_sio_write(dev, 0xf9 , 0x48 );
- it_sio_write(dev, 0xfa , 0x00 );
- it_sio_write(dev, 0xfb , 0x00 );
+ it_sio_write(dev, 0xf1, 0x40);
+ it_sio_write(dev, 0xf4, 0x80);
+ it_sio_write(dev, 0xf5, 0x00);
+ it_sio_write(dev, 0xf6, 0xf0);
+ it_sio_write(dev, 0xf9, 0x48);
+ it_sio_write(dev, 0xfa, 0x00);
+ it_sio_write(dev, 0xfb, 0x00);
ite_exit_conf(dev);
}
static void ite_gpio_conf(pnp_devfn_t dev)
{
ite_enter_conf (dev);
- it_sio_write (dev, 0x25 , 0x80 );
- it_sio_write (dev, 0x26 , 0x07 );
- it_sio_write (dev, 0x28 , 0x81 );
- it_sio_write (dev, 0x2c , 0x06 );
- it_sio_write (dev, 0x72 , 0x00 );
- it_sio_write (dev, 0x73 , 0x00 );
- it_sio_write (dev, 0xb3 , 0x01 );
- it_sio_write (dev, 0xb8 , 0x00 );
- it_sio_write (dev, 0xc0 , 0x00 );
- it_sio_write (dev, 0xc3 , 0x00 );
- it_sio_write (dev, 0xc8 , 0x00 );
- it_sio_write (dev, 0xc9 , 0x07 );
- it_sio_write (dev, 0xcb , 0x01 );
- it_sio_write (dev, 0xf0 , 0x10 );
- it_sio_write (dev, 0xf4 , 0x27 );
- it_sio_write (dev, 0xf8 , 0x20 );
- it_sio_write (dev, 0xf9 , 0x01 );
- ite_exit_conf (dev);
+ it_sio_write(dev, 0x25, 0x80);
+ it_sio_write(dev, 0x26, 0x07);
+ it_sio_write(dev, 0x28, 0x81);
+ it_sio_write(dev, 0x2c, 0x06);
+ it_sio_write(dev, 0x72, 0x00);
+ it_sio_write(dev, 0x73, 0x00);
+ it_sio_write(dev, 0xb3, 0x01);
+ it_sio_write(dev, 0xb8, 0x00);
+ it_sio_write(dev, 0xc0, 0x00);
+ it_sio_write(dev, 0xc3, 0x00);
+ it_sio_write(dev, 0xc8, 0x00);
+ it_sio_write(dev, 0xc9, 0x07);
+ it_sio_write(dev, 0xcb, 0x01);
+ it_sio_write(dev, 0xf0, 0x10);
+ it_sio_write(dev, 0xf4, 0x27);
+ it_sio_write(dev, 0xf8, 0x20);
+ it_sio_write(dev, 0xf9, 0x01);
+ ite_exit_conf(dev);
}
void board_BeforeAgesa(struct sysinfo *cb)
diff --git a/src/mainboard/esd/atom15/romstage.c b/src/mainboard/esd/atom15/romstage.c
index 3aa02d8..c89a1e2 100644
--- a/src/mainboard/esd/atom15/romstage.c
+++ b/src/mainboard/esd/atom15/romstage.c
@@ -57,7 +57,7 @@
read_ssus_gpio(27),
read_ssus_gpio(28),
read_ssus_gpio(29),
- read_ssus_gpio(30) );
+ read_ssus_gpio(30));
}
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index de90fda..a0e9631 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -226,7 +226,7 @@
* pm_iowrite(0x55, byte);
*
* byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
+ * byte &= ~(1 << 6);
* pm_iowrite(0x67, byte);
*/
}
diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
index c07465c..e1850d2 100644
--- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c
+++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
@@ -123,7 +123,7 @@
#define WLSEED 0x08
#define RXSEED 0x40
WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
- HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
+ HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
PSO_END
};
diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
index fd3a821..512aea5 100644
--- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
+++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
@@ -111,7 +111,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c
index 92ef836..f9e4e3e 100644
--- a/src/mainboard/google/cyan/variants/banon/gpio.c
+++ b/src/mainboard/google/cyan/variants/banon/gpio.c
@@ -66,7 +66,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -127,9 +127,9 @@
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
GPIO_NC, /* 80 SATA_GP3 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -156,7 +156,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c
index d011428..b4d8b1e 100644
--- a/src/mainboard/google/cyan/variants/celes/gpio.c
+++ b/src/mainboard/google/cyan/variants/celes/gpio.c
@@ -66,13 +66,13 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */
GPI(trig_edge_both, L1, P_20K_H, non_maskable,
- en_edge_detect, NA , NA),
+ en_edge_detect, NA, NA),
/* 81 SDMMC3_CD_B */
GPIO_NC, /* 82 spkr assumed gpio number */
Native_M1, /* 83 SUSPWRDNACK */
@@ -132,7 +132,7 @@
GPIO_NC, /* 78 SATA_GP2 */
GPIO_NC, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- GPIO_NC, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ GPIO_NC, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_NC, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -159,7 +159,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c
index bf869fe..4cdfcdf 100644
--- a/src/mainboard/google/cyan/variants/cyan/gpio.c
+++ b/src/mainboard/google/cyan/variants/cyan/gpio.c
@@ -66,7 +66,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -130,7 +130,7 @@
GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */
Native_M1, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -159,7 +159,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c
index d9d2648..2010ac5 100644
--- a/src/mainboard/google/cyan/variants/edgar/gpio.c
+++ b/src/mainboard/google/cyan/variants/edgar/gpio.c
@@ -66,7 +66,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -129,7 +129,7 @@
GPIO_NC, /* 78 SATA_GP2 */
Native_M1, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
GPIO_INPUT_PU_20K, /* 90 PCIE_CLKREQ0B */
@@ -156,7 +156,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c
index 76549ba4..d628658 100644
--- a/src/mainboard/google/cyan/variants/kefka/gpio.c
+++ b/src/mainboard/google/cyan/variants/kefka/gpio.c
@@ -67,7 +67,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -129,7 +129,7 @@
GPIO_NC, /* 78 SATA_GP2 */
Native_M1, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
GPIO_NC, /* 90 PCIE_CLKREQ0B */
@@ -156,7 +156,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c
index 1a9e540..7b9b5af 100644
--- a/src/mainboard/google/cyan/variants/reks/gpio.c
+++ b/src/mainboard/google/cyan/variants/reks/gpio.c
@@ -66,7 +66,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -129,9 +129,9 @@
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN-> EC_IN_RW */
GPIO_NC, /* 80 SATA_GP3 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -158,7 +158,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c
index 6c1dbdc..95c1300 100644
--- a/src/mainboard/google/cyan/variants/relm/gpio.c
+++ b/src/mainboard/google/cyan/variants/relm/gpio.c
@@ -67,7 +67,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -130,9 +130,9 @@
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
GPIO_NC, /* 80 SATA_GP3 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -159,7 +159,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c
index df1bff1..1307f7d 100644
--- a/src/mainboard/google/cyan/variants/setzer/gpio.c
+++ b/src/mainboard/google/cyan/variants/setzer/gpio.c
@@ -67,7 +67,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -128,9 +128,9 @@
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
GPIO_NC, /* 78 SATA_GP2 */
- Native_M1, /* 79 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 79 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID3 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
GPIO_NC, /* 90 PCIE_CLKREQ0B */
@@ -157,7 +157,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c
index 8328edd..b4feebf 100644
--- a/src/mainboard/google/cyan/variants/terra/gpio.c
+++ b/src/mainboard/google/cyan/variants/terra/gpio.c
@@ -66,7 +66,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -128,7 +128,7 @@
GPIO_NC, /* 78 SATA_GP2 */
GPIO_NC, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -155,7 +155,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c
index c6875b4..43f1099 100644
--- a/src/mainboard/google/cyan/variants/ultima/gpio.c
+++ b/src/mainboard/google/cyan/variants/ultima/gpio.c
@@ -66,7 +66,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -129,9 +129,9 @@
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN-> EC_IN_RW */
GPIO_NC, /* 80 SATA_GP3 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -158,7 +158,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c
index 3611439..3d3b273 100644
--- a/src/mainboard/google/cyan/variants/wizpig/gpio.c
+++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c
@@ -66,7 +66,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -128,9 +128,9 @@
GPIO_NC, /* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
GPIO_NC, /* 78 SATA_GP2 */
- Native_M1, /* 79 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 79 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
GPIO_NC, /* 90 PCIE_CLKREQ0B */
@@ -157,7 +157,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c
index 6f8ff0f..975eea5 100644
--- a/src/mainboard/google/eve/romstage.c
+++ b/src/mainboard/google/eve/romstage.c
@@ -27,7 +27,7 @@
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
/* DQ byte map */
const u8 dq_map[2][12] = {
- { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c
index 297b149..4fe88ef 100644
--- a/src/mainboard/google/glados/variants/lars/variant.c
+++ b/src/mainboard/google/glados/variants/lars/variant.c
@@ -33,9 +33,9 @@
{
/* DQ byte map */
const u8 dq_map[2][12] = {
- { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
- { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
/* DQS CPU<>DRAM map */
const u8 dqs_map[2][8] = {
diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c
index aaa8ae7..5b2985a 100644
--- a/src/mainboard/google/gru/boardid.c
+++ b/src/mainboard/google/gru/boardid.c
@@ -65,7 +65,7 @@
}
}
- die("Read impossible value ( > 1023) from 10-bit ADC!");
+ die("Read impossible value (> 1023) from 10-bit ADC!");
}
uint32_t board_id(void)
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index 8b8000c..8bd758b 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -295,7 +295,7 @@
index = run(index);
auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8;
auxout[1] = 0x0a840000;
- /*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/
+ /*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/
auxout[2] = 0x00000000;
auxout[3] = 0x01000000;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
index a82ddf9..201198d 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
@@ -112,7 +112,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index ed79dad..7ab5eb1 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -365,9 +365,9 @@
#define SCI_MAP_PWRBTN 0x73
SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
- {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},
- {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},
- {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},
+ {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE},
+ {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE},
+ {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE},
{SCI_MAP_OHCI_12_0, PME_GPE},
{SCI_MAP_OHCI_13_0, PME_GPE},
{SCI_MAP_XHCI_10_0, PME_GPE},
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c
index d988023..199a15e 100644
--- a/src/mainboard/intel/bayleybay_fsp/romstage.c
+++ b/src/mainboard/intel/bayleybay_fsp/romstage.c
@@ -65,67 +65,67 @@
/*
*ALC262 Verb Table - 10EC0262
*/
- /* Pin Complex (NID 0x11 ) */
+ /* Pin Complex (NID 0x11) */
0x01171CF0,
0x01171D11,
0x01171E11,
0x01171F41,
- /* Pin Complex (NID 0x12 ) */
+ /* Pin Complex (NID 0x12) */
0x01271CF0,
0x01271D11,
0x01271E11,
0x01271F41,
- /* Pin Complex (NID 0x14 ) */
+ /* Pin Complex (NID 0x14) */
0x01471C10,
0x01471D40,
0x01471E01,
0x01471F01,
- /* Pin Complex (NID 0x15 ) */
+ /* Pin Complex (NID 0x15) */
0x01571CF0,
0x01571D11,
0x01571E11,
0x01571F41,
- /* Pin Complex (NID 0x16 ) */
+ /* Pin Complex (NID 0x16) */
0x01671CF0,
0x01671D11,
0x01671E11,
0x01671F41,
- /* Pin Complex (NID 0x18 ) */
+ /* Pin Complex (NID 0x18) */
0x01871C20,
0x01871D98,
0x01871EA1,
0x01871F01,
- /* Pin Complex (NID 0x19 ) */
+ /* Pin Complex (NID 0x19) */
0x01971C21,
0x01971D98,
0x01971EA1,
0x01971F02,
- /* Pin Complex (NID 0x1A ) */
+ /* Pin Complex (NID 0x1A) */
0x01A71C2F,
0x01A71D30,
0x01A71E81,
0x01A71F01,
- /* Pin Complex (NID 0x1B ) */
+ /* Pin Complex (NID 0x1B) */
0x01B71C1F,
0x01B71D40,
0x01B71E21,
0x01B71F02,
- /* Pin Complex (NID 0x1C ) */
+ /* Pin Complex (NID 0x1C) */
0x01C71CF0,
0x01C71D11,
0x01C71E11,
0x01C71F41,
- /* Pin Complex (NID 0x1D ) */
+ /* Pin Complex (NID 0x1D) */
0x01D71C01,
0x01D71DC6,
0x01D71E14,
0x01D71F40,
- /* Pin Complex (NID 0x1E ) */
+ /* Pin Complex (NID 0x1E) */
0x01E71CF0,
0x01E71D11,
0x01E71E11,
0x01E71F41,
- /* Pin Complex (NID 0x1F ) */
+ /* Pin Complex (NID 0x1F) */
0x01F71CF0,
0x01F71D11,
0x01F71E11,
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
index 4e2f31f..31f5452 100644
--- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
+++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
@@ -23,7 +23,7 @@
{
/* DQ byte map Ch0 */
const u8 dq_map[12] = {
- 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,
+ 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 38af2b8..f6c867a 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -261,7 +261,7 @@
/* For reference print FSP version */
u32 version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "FSP Version %d.%d.%d Build %d\n",
- version >> 24 , (version >> 16) & 0xff,
+ version >> 24, (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c
index 676f84d..fc0581c 100644
--- a/src/mainboard/intel/kunimitsu/spd/spd_util.c
+++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c
@@ -26,9 +26,9 @@
{
/* DQ byte map */
const u8 dq_map[2][12] = {
- { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
- { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
}
diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c
index fa24594..ed9ae4b 100644
--- a/src/mainboard/intel/strago/gpio.c
+++ b/src/mainboard/intel/strago/gpio.c
@@ -69,7 +69,7 @@
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
- GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@@ -131,11 +131,11 @@
GPIO_OUT_HIGH, /* 75 SATA_GP0 */
GPIO_NC,
/* 76 GPI SATA_GP1 */
- GPIO_INPUT_PU_20K, /* 77 SATA_LEDN , EC_IN_RW */
+ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */
GPIO_NC, /* 80 SATA_GP3 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
- Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+ Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -162,7 +162,7 @@
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
- GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c
index a82ddf9..201198d 100644
--- a/src/mainboard/lenovo/g505s/BiosCallOuts.c
+++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c
@@ -112,7 +112,7 @@
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index 9ef46d5..3eaa8b0 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -365,9 +365,9 @@
#define SCI_MAP_PWRBTN 0x73
SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
- {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},
- {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},
- {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},
+ {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE},
+ {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE},
+ {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE},
{SCI_MAP_OHCI_12_0, PME_GPE},
{SCI_MAP_OHCI_13_0, PME_GPE},
{SCI_MAP_XHCI_10_0, PME_GPE},
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index b409b5e..203044e3 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -43,7 +43,7 @@
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 0, 0 }, /* P0: , OC 0 */
+ { 1, 0, 0 }, /* P0:, OC 0 */
{ 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */
{ 1, 1, 3 }, /* P2: OC 3 */
{ 1, 0, -1 }, /* P3: no OC */
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index e4a8efb..3d4baa5 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -183,7 +183,7 @@
/* We want early GPIO setup, to be able to detect legacy I/O module */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
/* Enable GPIOs */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
dock_err = dlpc_init();
diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c
index 7707d62..bccb7f1 100644
--- a/src/mainboard/lenovo/t60/smihandler.c
+++ b/src/mainboard/lenovo/t60/smihandler.c
@@ -49,7 +49,7 @@
{
u8 *bar;
if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
- printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL));
+ printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
*(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;
if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)
*(bar+LVTMA_BL_MOD_LEVEL) += 0x10;
diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c
index 5b49498..f55428e 100644
--- a/src/mainboard/lenovo/x60/dock.c
+++ b/src/mainboard/lenovo/x60/dock.c
@@ -190,7 +190,7 @@
dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00);
dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00);
dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP |
- PC87392_GPIO_PIN_OE , 0x00);
+ PC87392_GPIO_PIN_OE, 0x00);
dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00);
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index 94c8a8f..d5dc9f5 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -183,7 +183,7 @@
/* We want early GPIO setup, to be able to detect legacy I/O module */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
/* Enable GPIOs */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
dock_err = dlpc_init();
diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c
index d98a809..b93f48e 100644
--- a/src/mainboard/lenovo/z61t/smihandler.c
+++ b/src/mainboard/lenovo/z61t/smihandler.c
@@ -50,7 +50,7 @@
{
u8 *bar;
if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
- printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar,
+ printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar,
*(bar+LVTMA_BL_MOD_LEVEL));
*(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;
if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)
diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c
index 3866035..cc25957 100644
--- a/src/mainboard/lippert/frontrunner-af/mainboard.c
+++ b/src/mainboard/lippert/frontrunner-af/mainboard.c
@@ -65,19 +65,19 @@
/* Init Hudson GPIOs. */
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
- FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
- FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
+ FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
+ FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU)
- FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
- FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
- FCH_IOMUX( 57) = 1;
- FCH_GPIO ( 57) = 0x28;
- FCH_IOMUX( 58) = 1;
- FCH_GPIO ( 58) = 0x28;
- FCH_IOMUX( 96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
- FCH_IOMUX( 52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector
- FCH_IOMUX( 61) = 2; // default to inputs with int. PU
- FCH_IOMUX( 62) = 2;
+ FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0
+ FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
+ FCH_IOMUX(57) = 1;
+ FCH_GPIO (57) = 0x28;
+ FCH_IOMUX(58) = 1;
+ FCH_GPIO (58) = 0x28;
+ FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
+ FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector
+ FCH_IOMUX(61) = 2; // default to inputs with int. PU
+ FCH_IOMUX(62) = 2;
FCH_IOMUX(187) = 2;
FCH_IOMUX(188) = 2;
FCH_IOMUX(189) = 1;
diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c
index 3de388b..cea5350 100644
--- a/src/mainboard/lippert/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/toucan-af/mainboard.c
@@ -33,16 +33,16 @@
/* Init Hudson GPIOs. */
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
- FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
- FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
+ FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
+ FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS#
FCH_GPIO (197) = 0x28; // = input, disable int. pull-up
- FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
- FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
- FCH_IOMUX( 57) = 1;
- FCH_GPIO ( 57) = 0x28;
- FCH_IOMUX( 58) = 1;
- FCH_GPIO ( 58) = 0x28;
+ FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0
+ FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
+ FCH_IOMUX(57) = 1;
+ FCH_GPIO (57) = 0x28;
+ FCH_IOMUX(58) = 1;
+ FCH_GPIO (58) = 0x28;
FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector
FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0
FCH_IOMUX(188) = 2;
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
index c5ceb75..9c744ce 100644
--- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
+++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
@@ -101,12 +101,12 @@
}
for (i = 2; i < 8; i++) {
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+ dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
}
}
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 8538d33..4555bf9 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -87,13 +87,13 @@
u32 dword;
u8 byte;
- byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+ byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+ pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
}
static const u8 spd_addr[] = {
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 8fe2dc0..e482840 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -44,7 +44,7 @@
* 4banks (2)
* SSTL_2 (2)
* 4th GEN die (C)
- * Normal Power Consumption (<blank> )
+ * Normal Power Consumption (<blank>)
* TSOP (T)
* Single Die (<blank>)
* Lead Free (P)
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index da3913d..9bb9c00 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -42,7 +42,7 @@
* 4banks (2)
* SSTL_2 (2)
* 4th GEN die (C)
- * Normal Power Consumption (<blank> )
+ * Normal Power Consumption (<blank>)
* TSOP (T)
* Single Die (<blank>)
* Lead Free (P)
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c
index 330531f..9febec7 100644
--- a/src/mainboard/pcengines/apu1/OemCustomize.c
+++ b/src/mainboard/pcengines/apu1/OemCustomize.c
@@ -108,7 +108,7 @@
#define WLSEED 0x08
#define RXSEED 0x40
WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
- HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
+ HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
PSO_END
};
diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c
index 74c3b7b..7a988e7 100644
--- a/src/mainboard/pcengines/apu1/gpio_ftns.c
+++ b/src/mainboard/pcengines/apu1/gpio_ftns.c
@@ -25,9 +25,9 @@
uintptr_t base_addr = 0;
/* Find the ACPImmioAddr base address */
- for ( pm_index = 0x27; pm_index > 0x23; pm_index-- ) {
- outb( pm_index, PM_INDEX );
- pm_data = inb( PM_DATA );
+ for (pm_index = 0x27; pm_index > 0x23; pm_index--) {
+ outb(pm_index, PM_INDEX);
+ pm_data = inb(PM_DATA);
base_addr <<= 8;
base_addr |= (u32)pm_data;
}
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index 8e2636b..1c7b4fd 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -99,7 +99,7 @@
FchParams->Usb.Ehci1Enable = TRUE;
}
- // Enable EHCI 1 ( port 4 to 7)
+ // Enable EHCI 1 (port 4 to 7)
// port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
FchParams->Usb.Ehci2Enable = TRUE;
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
index 9434b93..99ddf80 100644
--- a/src/mainboard/pcengines/apu2/mainboard.c
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -167,12 +167,12 @@
//
// Enable the RTC output
//
- pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11));
+ pm_write16(PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11));
//
// Enable power on from WAKE#
//
- pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14));
+ pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14));
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c
index 89bc2939..8143a16 100644
--- a/src/mainboard/siemens/mc_tcu3/ptn3460.c
+++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c
@@ -53,7 +53,7 @@
hwi_block);
return 1;
}
- if (hwilib_get_field(PF_Color_Depth ,&color_depth, 1) != 1) {
+ if (hwilib_get_field(PF_Color_Depth, &color_depth, 1) != 1) {
printk(BIOS_ERR, "LCD: Missing panel features from %s\n",
hwi_block);
return 1;
diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c
index 628e88b9..ef07f7e 100644
--- a/src/mainboard/siemens/mc_tcu3/romstage.c
+++ b/src/mainboard/siemens/mc_tcu3/romstage.c
@@ -66,67 +66,67 @@
/*
*ALC262 Verb Table - 10EC0262
*/
- /* Pin Complex (NID 0x11 ) */
+ /* Pin Complex (NID 0x11) */
0x01171CF0,
0x01171D11,
0x01171E11,
0x01171F41,
- /* Pin Complex (NID 0x12 ) */
+ /* Pin Complex (NID 0x12) */
0x01271CF0,
0x01271D11,
0x01271E11,
0x01271F41,
- /* Pin Complex (NID 0x14 ) */
+ /* Pin Complex (NID 0x14) */
0x01471C10,
0x01471D40,
0x01471E01,
0x01471F01,
- /* Pin Complex (NID 0x15 ) */
+ /* Pin Complex (NID 0x15) */
0x01571CF0,
0x01571D11,
0x01571E11,
0x01571F41,
- /* Pin Complex (NID 0x16 ) */
+ /* Pin Complex (NID 0x16) */
0x01671CF0,
0x01671D11,
0x01671E11,
0x01671F41,
- /* Pin Complex (NID 0x18 ) */
+ /* Pin Complex (NID 0x18) */
0x01871C20,
0x01871D98,
0x01871EA1,
0x01871F01,
- /* Pin Complex (NID 0x19 ) */
+ /* Pin Complex (NID 0x19) */
0x01971C21,
0x01971D98,
0x01971EA1,
0x01971F02,
- /* Pin Complex (NID 0x1A ) */
+ /* Pin Complex (NID 0x1A) */
0x01A71C2F,
0x01A71D30,
0x01A71E81,
0x01A71F01,
- /* Pin Complex (NID 0x1B ) */
+ /* Pin Complex (NID 0x1B) */
0x01B71C1F,
0x01B71D40,
0x01B71E21,
0x01B71F02,
- /* Pin Complex (NID 0x1C ) */
+ /* Pin Complex (NID 0x1C) */
0x01C71CF0,
0x01C71D11,
0x01C71E11,
0x01C71F41,
- /* Pin Complex (NID 0x1D ) */
+ /* Pin Complex (NID 0x1D) */
0x01D71C01,
0x01D71DC6,
0x01D71E14,
0x01D71F40,
- /* Pin Complex (NID 0x1E ) */
+ /* Pin Complex (NID 0x1E) */
0x01E71CF0,
0x01E71D11,
0x01E71E11,
0x01E71F41,
- /* Pin Complex (NID 0x1F ) */
+ /* Pin Complex (NID 0x1F) */
0x01F71CF0,
0x01F71D11,
0x01F71E11,
diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
index b2bc0dd..58b5ba4 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
@@ -99,12 +99,12 @@
}
for(i = 2; i < 8; i++) {
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+ dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
}
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
index 75b1347..b319558 100644
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
@@ -105,12 +105,12 @@
}
for(i = 2; i < 8; i++) {
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+ dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
}
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 6aa20bb..e51cf19 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -89,17 +89,17 @@
// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+ pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4);
dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword);
}
static const u8 spd_addr[] = {
@@ -113,7 +113,7 @@
/* third node */
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
/* fourth node */
- RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
+ RC03, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index 09704f8..7164940 100644
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -98,12 +98,12 @@
}
for(i = 2; i < 8; i++) {
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+ dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
}
}
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 7c4fd5b..2d302f1 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -87,18 +87,18 @@
uint32_t dword;
uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+ pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
/*serial 0 */
dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4);
dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword);
}
static const u8 spd_addr[] = {
diff --git a/src/northbridge/amd/agesa/family12/dimmSpd.c b/src/northbridge/amd/agesa/family12/dimmSpd.c
index 2f0af59..a0a1aea6 100644
--- a/src/northbridge/amd/agesa/family12/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family12/dimmSpd.c
@@ -55,7 +55,7 @@
IN UINT32 Func,
IN UINTN Data,
IN OUT AGESA_READ_SPD_PARAMS *SpdData
- )
+ )
{
UINT8 SmBusAddress = 0;
UINTN Index;
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index ae5b227..0a56d18 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -149,7 +149,7 @@
/* Ext conf space */
if (!reg) {
/* Because of Extend conf space, we will never run out of reg,
- * but we need one index to differ them. So ,same node and same
+ * but we need one index to differ them. So,same node and same
* link can have multi range
*/
u32 index = get_io_addr_index(nodeid, link);
@@ -185,7 +185,7 @@
/* Ext conf space */
if (!reg) {
/* Because of Extend conf space, we will never run out of reg,
- * but we need one index to differ them. So ,same node and same
+ * but we need one index to differ them. So,same node and same
* link can have multi range
*/
u32 index = get_mmio_addr_index(nodeid, link);
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 2488dfc..91103ff 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -1737,7 +1737,7 @@
* and PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3).
*/
- u8 ChipSel, Rows, Cols, Ranks ,Banks, DevWidth;
+ u8 ChipSel, Rows, Cols, Ranks, Banks, DevWidth;
u32 BankAddrReg, csMask;
u32 val;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index f62aa15..b62661b 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -684,7 +684,7 @@
{tempW = bitTestSet(tempW, 7);}
if (bitTest(tempW1,18))
{tempW = bitTestSet(tempW, 6);}
- /* tempW = tempW|(((tempW1 >> 20) & 0x7 )<< 3); */
+ /* tempW = tempW|(((tempW1 >> 20) & 0x7)<< 3); */
tempW = tempW|((tempW1&0x00700000) >> 17);
/* workaround for DR-B0 */
if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED]))
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index c085c87..f3a27e2 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -148,7 +148,8 @@
printk(BIOS_DEBUG, "\n");
for (device = 1; device < 0x80; device++) {
int j;
- if ( spd_read_byte(device, 0) < 0 ) continue;
+ if (spd_read_byte(device, 0) < 0)
+ continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
for (j = 0; j < 256; j++) {
int status;
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c
index 72b2761..94855cf 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.c
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c
@@ -131,7 +131,7 @@
mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10);
if (bmbound_hi > 0x100000000) {
- ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10 );
+ ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20);
}
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 21767b9..221d71f 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -180,7 +180,7 @@
*/
u32 version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
- version >> 24 , (version >> 16) & 0xff,
+ version >> 24, (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
report_memory_config();
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 59c7741..ac0ed45 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -36,7 +36,7 @@
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80);
printk(BIOS_DEBUG, " done.\n");
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 33f9c48..3160039 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -1420,7 +1420,7 @@
TOM = 4032;
TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64);
TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64)
- , TOUUD), 64);
+ , TOUUD), 64);
memory_remap = 0;
if (TOUUD - TOLUD > 64) {
memory_remap = 1;
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 3984fb7..7f90529 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -181,9 +181,9 @@
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */
+ pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */
pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
- pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */
+ pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */
pci_write_config32(LPC, 0x88, 0x007c0291);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 5adf865..778b2f7 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -57,13 +57,13 @@
#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)
#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0)
-#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \
+#define ONLY_DIMMA_IS_POPULATED(dimms, ch) (\
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \
!DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))
-#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \
+#define ONLY_DIMMB_IS_POPULATED(dimms, ch) (\
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \
!DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2)))
-#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \
+#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) (\
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))))
#define FOR_EACH_DIMM(idx) \
@@ -905,11 +905,11 @@
reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9);
reg32 |= ((u32) pll->dbsel[f][clk]) << dqs;
MCHBAR32(0x5b4+rank*4) = (MCHBAR32(0x5b4+rank*4) &
- ~( (1 << (dqs+9))|(1 << dqs) )) | reg32;
+ ~((1 << (dqs+9))|(1 << dqs))) | reg32;
reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs*2) + 16);
MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &
- ~( (1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)) )) | reg32;
+ ~((1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)))) | reg32;
reg8 = pll->pi[f][clk];
MCHBAR8(0x520+j) = (MCHBAR8(0x520+j) & ~0x3f) | reg8;
@@ -930,11 +930,11 @@
reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9);
reg32 |= ((u32) pll->dbsel[f][clk]) << dq;
MCHBAR32(0x5a4+rank*4) = (MCHBAR32(0x5a4+rank*4) &
- ~( (1 << (dq+9))|(1 << dq) )) | reg32;
+ ~((1 << (dq+9))|(1 << dq))) | reg32;
reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2);
MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &
- ~( (1 << (dq*2 + 1))|(1 << (dq*2)) )) | reg32;
+ ~((1 << (dq*2 + 1))|(1 << (dq*2)))) | reg32;
reg8 = pll->pi[f][clk];
MCHBAR8(0x500+j) = (MCHBAR8(0x500+j) & ~0x3f) | reg8;
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 88d8bd6..20f3038 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -225,7 +225,7 @@
* FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
* XP : | 3 | 4 | 4 | 5 | 6 | 7 | 8 | 8 |
*/
- static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 , 8, 8 };
+ static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7, 8, 8 };
xp = frq_xp_map[get_FRQ(tCK, 133) - 3];
}
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 0c3751f..1975051 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -248,7 +248,7 @@
*/
u32 version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
- version >> 24 , (version >> 16) & 0xff,
+ version >> 24, (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
/* Send ME init done for SandyBridge here. This is done
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index fbdb4f9..d5526f6 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -463,7 +463,7 @@
struct rt_dqs_setting dqs_setting[TOTAL_BYTELANES];
u16 saved_dqs_center[TOTAL_CHANNELS][TOTAL_BYTELANES];
- memset(saved_dqs_center, 0 , sizeof(saved_dqs_center));
+ memset(saved_dqs_center, 0, sizeof(saved_dqs_center));
printk(BIOS_DEBUG, "Starting DQS read training\n");
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index 254be7b..494d78a 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -105,15 +105,15 @@
* 0000: 66MHz
* 0001: 100MHz
* 0010: 133MHz
- * 0011: 200MHz ( DDR200 )
- * 0100: 266MHz ( DDR266 )
- * 0101: 333MHz ( DDR333 )
- * 0110: 400MHz ( DDR400 )
- * 0111: 533MHz ( DDR I/II 533)
- * 1000: 667MHz ( DDR I/II 667)
- * 1001: 800MHz ( DDR3 800)
- * 1010: 1066MHz ( DDR3 1066)
- * 1011: 1333MHz ( DDR3 1333)
+ * 0011: 200MHz (DDR200)
+ * 0100: 266MHz (DDR266)
+ * 0101: 333MHz (DDR333)
+ * 0110: 400MHz (DDR400)
+ * 0111: 533MHz (DDR I/II 533)
+ * 1000: 667MHz (DDR I/II 667)
+ * 1001: 800MHz (DDR3 800)
+ * 1010: 1066MHz (DDR3 1066)
+ * 1011: 1333MHz (DDR3 1333)
* Bit[3:0]
* N: Frame Buffer Size 2^N MB
*/
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c
index ff5dc87..e00ae91 100644
--- a/src/soc/broadcom/cygnus/ddr_init.c
+++ b/src/soc/broadcom/cygnus/ddr_init.c
@@ -70,70 +70,91 @@
uint32_t readvalue = 0;
// Disable low power receivers: bit 0 of the byte lane STATIC_PAD_CTL register
- readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL);
- reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));
+ readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL);
+ reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL,
+ (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));
// Turn off ZQ_CAL drivers: bits 0,1, and 17 of the ZQ_CAL register (other bits 0 & 1 are set to 1)
- readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL);
- reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ)));
+ readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL);
+ reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL,
+ (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ)));
// Byte lane 0 power up
- readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
- reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));
+ readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
+ reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
+ (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));
- readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
- reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f));
+ readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
+ reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
+ (readvalue & 0xffff800f));
- readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
- reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));
+ readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
+ reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
+ (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));
// Byte lane 1 power up
- readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
- reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));
+ readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
+ reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
+ (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));
- readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
- reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f));
+ readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
+ reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
+ (readvalue & 0xffff800f));
- readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
- reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));
+ readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
+ reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
+ (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));
// Turn on PHY_CONTROL AUTO_OEB C not required
// Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a
printk(BIOS_INFO, "\n....PLL power up.\n");
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN)));
+ reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
+ (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
+ ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN)));
// PLL out of reset
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET)));
+ reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
+ (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
+ ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET)));
printk(BIOS_INFO, "\n....poll lock..\n");
// Poll lock
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS);
- while ( ( readvalue & 0x1) == 0x0 )
+ while ((readvalue & 0x1) == 0x0)
{
printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_PLL_STATUS = %8x..\n",readvalue);
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS);
}
printk(BIOS_INFO, "\n....after while..\n");
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV)));
+ reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
+ (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
+ ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV)));
printk(BIOS_INFO, "\n....remove hold..\n");
// Remove hold
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD)));
+ reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
+ (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
+ ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD)));
printk(BIOS_INFO, "\n....restore dac..\n");
// Restore DAC
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff));
+ reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL,
+ (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff));
printk(BIOS_INFO, "\n....set iddq bit..\n");
// Set the iddq bit in the idle control register and select all outputs except cke and rst in the idee select registers.
// Do NOT assert any other bits in the idle control register. (This step can be done during init on power up.)
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ)));
+ reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL,
+ (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &
+ ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ)));
printk(BIOS_INFO, "\n....idle pad enable 0..\n");
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, 0x0);
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, 0x0);
printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL..\n");
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE)));
+ reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL,
+ (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &
+ ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE)));
}
#endif
@@ -143,7 +164,7 @@
{
uint32_t val;
-#define SET_OVR_STEP(v) ( 0x30000 | ( (v) & 0x3F ) ) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */
+#define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */
val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN);
val = SET_OVR_STEP(val & 0xff);
@@ -441,27 +462,27 @@
/*DDR_SHMOO_RELATED_CHANGE*/
#ifdef CONFIG_RUN_DDR_SHMOO
-int ReWriteModeRegisters( void )
+int ReWriteModeRegisters(void)
{
int nRet = 0;
int j = 100;
- reg32_clear_bits( (volatile uint32_t *)DDR_DENALI_CTL_89 , 1 << 18 );
+ reg32_clear_bits((volatile uint32_t *)DDR_DENALI_CTL_89, 1 << 18);
/* Set mode register for MR0, MR1, MR2 and MR3 write for all chip selects */
- reg32_write( (volatile uint32_t *)DDR_DENALI_CTL_43 , (1 << 17) | (1 << 24) | (1 << 25) );
+ reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25));
/* Trigger Mode Register Write(MRW) sequence */
- reg32_set_bits( (volatile uint32_t *)DDR_DENALI_CTL_43 , 1 << 25 );
+ reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_43, 1 << 25);
do {
- if ( reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) {
+ if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) {
break;
}
--j;
- } while ( j );
+ } while (j);
- if ( j == 0 && (reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) == 0 ) {
+ if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) {
printk(BIOS_ERR, "Error: DRAM mode registers write failed\n");
nRet = 1;
};
@@ -975,25 +996,24 @@
) {
val |= (1 << 17); /* Force Override */
}
- // printk(BIOS_INFO, "Writing 0x%x to 0x%x\n",val,reg);
- reg32_write(reg,val);
+ // printk(BIOS_INFO, "Writing 0x%x to 0x%x\n",val,reg);
+ reg32_write(reg, val);
- reg32_read(reg); /* Dummy read back */
- }
- printk(BIOS_INFO, "done\n");
+ reg32_read(reg); /* Dummy read back */
+ }
+ printk(BIOS_INFO, "done\n");
- /* Perform memory test to see if the parameters work */
- if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0 ) {
- printk(BIOS_INFO, "Running simple memory test ..... ");
- i = simple_memory_test(
- (void *)CONFIG_SHMOO_REUSE_MEMTEST_START,
- CONFIG_SHMOO_REUSE_MEMTEST_LENGTH);
- if (i) {
- printk(BIOS_ERR, "failed!\n");
- return 1;
- }
- printk(BIOS_INFO, "OK\n");
- }
+ /* Perform memory test to see if the parameters work */
+ if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) {
+ printk(BIOS_INFO, "Running simple memory test ..... ");
+ i = simple_memory_test((void *)CONFIG_SHMOO_REUSE_MEMTEST_START,
+ CONFIG_SHMOO_REUSE_MEMTEST_LENGTH);
+ if (i) {
+ printk(BIOS_ERR, "failed!\n");
+ return 1;
+ }
+ printk(BIOS_INFO, "OK\n");
+ }
return 0;
}
@@ -1116,9 +1136,11 @@
unsigned long start;
unsigned int i, val;
- reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1);
+ reg32_write((uint32_t *)DDR_BistConfig,
+ reg32_read((uint32_t *)DDR_BistConfig) & ~0x1);
- for ( i = 0; i < 1000; i++);
+ for (i = 0; i < 1000; i++)
+ ;
#if !defined(CONFIG_IPROC_P7)
reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF);
@@ -1377,10 +1399,10 @@
/* Wait for DDR PHY up */
for (i=0; i < 0x19000; i++) {
val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
- if ( val != 0) {
- printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val);
+ if (val != 0) {
+ printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val);
break; /* DDR PHY is up */
- }
+ }
}
if (i == 0x19000) {
@@ -1484,7 +1506,7 @@
/* Enable auto self-refresh */
reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57,
0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |
- 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R );
+ 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R);
reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58,
DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R);
@@ -1495,9 +1517,9 @@
/* Disable auto-self refresh */
reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57,
0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |
- 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R );
+ 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R);
reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58,
- 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R );
+ 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R);
#endif
/* Start the DDR */
@@ -1598,7 +1620,7 @@
/* SRX */
if (skip_shmoo)
{
- // Enter Self refresh (dummy) , to keep Denali happy
+ // Enter Self refresh (dummy), to keep Denali happy
reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x0a050505);
__udelay(200);
diff --git a/src/soc/broadcom/cygnus/phy_reg_access.c b/src/soc/broadcom/cygnus/phy_reg_access.c
index eb48133..ea82dde 100644
--- a/src/soc/broadcom/cygnus/phy_reg_access.c
+++ b/src/soc/broadcom/cygnus/phy_reg_access.c
@@ -15,17 +15,17 @@
uint32 REGRD (uint32 address) {
- volatile unsigned long data;
+ volatile unsigned long data;
- data = (* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address)));
- //printf("REGRD %08X=%08X\n", address, data);
- return data;
+ data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address)));
+ //printf("REGRD %08X=%08X\n", address, data);
+ return data;
}
uint32 REGWR (uint32 address, uint32 data) {
- ((* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address))) = data);
- //printf("REGWR %08X=%08X\n", address, data);
-// return SOC_E_NONE;
- return 0;
+ ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data);
+ //printf("REGWR %08X=%08X\n", address, data);
+ // return SOC_E_NONE;
+ return 0;
}
diff --git a/src/soc/broadcom/cygnus/usb.c b/src/soc/broadcom/cygnus/usb.c
index d95efd1..5b93604 100644
--- a/src/soc/broadcom/cygnus/usb.c
+++ b/src/soc/broadcom/cygnus/usb.c
@@ -47,7 +47,7 @@
struct bcm_phy_instance {
struct phy *generic_phy;
int port;
- int host_mode; /* 1 - Host , 0 - device */
+ int host_mode; /* 1 - Host, 0 - device */
int power; /* 1 -powered_on 0 -powered off */
struct regulator *vbus_supply;
};
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 7208e88..3e03ca5 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -229,7 +229,7 @@
static void byt_pciexp_scan_bridge(struct device *dev)
{
static const struct reg_script wait_for_link_active[] = {
- REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000),
+ REG_PCI_POLL32(LCTL, (1 << 29), (1 << 29), 50000),
REG_SCRIPT_END,
};
diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c
index 20a0664..6cddf76 100644
--- a/src/soc/intel/baytrail/perf_power.c
+++ b/src/soc/intel/baytrail/perf_power.c
@@ -221,7 +221,7 @@
E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2
E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en
E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en
-E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en
+E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en
E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en
E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en
E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 4d13539..ccd6c9f 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -24,7 +24,7 @@
static void pci_domain_set_resources(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
assign_resources(dev->link_list);
}
@@ -49,7 +49,7 @@
static void enable_dev(struct device *dev)
{
- printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n",
+ printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n",
__FILE__, __func__,
dev_name(dev), dev->path.type);
printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n",
@@ -384,7 +384,7 @@
static void pci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
- printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
+ printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n",
__FILE__, __func__, dev_name(dev), vendor, device);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 27903e8..195dba4 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -47,7 +47,7 @@
static void soc_core_init(struct device *cpu)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(cpu));
printk(BIOS_DEBUG, "Init Braswell core.\n");
@@ -219,7 +219,7 @@
{
struct bus *cpu_bus = dev->link_list;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
if (mp_init_with_smm(cpu_bus, &mp_ops))
diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c
index 44116a8..238f8db 100644
--- a/src/soc/intel/braswell/emmc.c
+++ b/src/soc/intel/braswell/emmc.c
@@ -36,7 +36,7 @@
{
struct soc_intel_braswell_config *config = dev->chip_info;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
printk(BIOS_DEBUG, "eMMC init\n");
reg_script_run_on_dev(dev, emmc_ops);
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index b329531..895d2ee 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -49,7 +49,7 @@
static void gfx_pre_vbios_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
gfx_run_script(dev, gpu_pre_vbios_script);
@@ -57,7 +57,7 @@
static void gfx_post_vbios_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
gfx_run_script(dev, gfx_post_vbios_script);
@@ -65,7 +65,7 @@
static void gfx_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
/* Pre VBIOS Init */
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 7c9f306..6338878 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -153,7 +153,7 @@
{
struct soc_intel_braswell_config *config = dev->chip_info;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
lpe_stash_firmware_info(dev);
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index aac953b..60ff49f 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -143,7 +143,7 @@
struct soc_intel_braswell_config *config = dev->chip_info;
int iosf_reg, nvs_index;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
printk(BIOS_SPEW, "%s - %s\n",
get_pci_class_name(dev),
diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c
index 1a127f4..efd891a 100644
--- a/src/soc/intel/braswell/pcie.c
+++ b/src/soc/intel/braswell/pcie.c
@@ -41,7 +41,7 @@
static void pcie_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
}
@@ -56,7 +56,7 @@
{
int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
switch (root_port_offset(dev)) {
@@ -99,7 +99,7 @@
static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
/* Set slot implemented. */
pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI);
@@ -137,7 +137,7 @@
static void pcie_enable(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
if (is_first_port(dev)) {
struct soc_intel_braswell_config *config = dev->chip_info;
@@ -162,7 +162,7 @@
static void pcie_root_set_subsystem(struct device *dev, unsigned int vid,
unsigned int did)
{
- printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
+ printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n",
__FILE__, __func__, dev_name(dev), vid, did);
uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff);
diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c
index 8052b29..2507641 100644
--- a/src/soc/intel/braswell/sata.c
+++ b/src/soc/intel/braswell/sata.c
@@ -30,7 +30,7 @@
static void sata_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
}
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index 122c67e..17fc685 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -29,7 +29,7 @@
struct resource *bar;
global_nvs_t *gnvs;
- printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x )\n",
+ printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n",
__FILE__, __func__, dev_name(dev), iosf_reg, nvs_index);
/* Find ACPI NVS to update BARs */
diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c
index 97c39b3..1775ce7 100644
--- a/src/soc/intel/braswell/sd.c
+++ b/src/soc/intel/braswell/sd.c
@@ -35,7 +35,7 @@
{
struct soc_intel_braswell_config *config = dev->chip_info;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
if (config == NULL)
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 14b412a..ca87d63 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -55,14 +55,14 @@
add_mmio_resource(struct device *dev, int i, unsigned long addr,
unsigned long size)
{
- printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n",
+ printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n",
__FILE__, __func__, dev_name(dev), addr, size);
mmio_resource(dev, i, addr >> 10, size >> 10);
}
static void sc_add_mmio_resources(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
@@ -102,7 +102,7 @@
{
struct resource *res;
- printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x, 0x%08x )\n",
+ printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x, 0x%08x)\n",
__FILE__, __func__, dev_name(dev), base, size, index);
if (io_range_in_default(base, size))
@@ -118,7 +118,7 @@
{
struct resource *res;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
/* Add the default claimed IO range for the LPC device. */
@@ -136,7 +136,7 @@
static void sc_read_resources(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
/* Get the normal PCI resources of this device. */
@@ -165,7 +165,7 @@
const struct soc_irq_route *ir = &global_soc_irq_route;
struct soc_intel_braswell_config *config = dev->chip_info;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
/* Set up the PIRQ PIC routing based on static config. */
@@ -206,7 +206,7 @@
uint32_t mask = 0;
uint32_t mask2 = 0;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
#define SET_DIS_MASK(name_) \
@@ -292,7 +292,7 @@
{
uint32_t reg8;
- printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x )\n",
+ printk(BIOS_SPEW, "%s/%s (%s, 0x%08x)\n",
__FILE__, __func__, dev_name(dev), offset);
printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
reg8 = pci_read_config8(dev, offset + 4);
@@ -309,7 +309,7 @@
{
void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
/* Need to set magic register 0x43 to 0xd7 in config space. */
@@ -331,7 +331,7 @@
{
unsigned int offset;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
/*
@@ -410,7 +410,7 @@
{
uint32_t reg32;
- printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ printk(BIOS_SPEW, "%s/%s (%s)\n",
__FILE__, __func__, dev_name(dev));
if (!dev->enabled) {
int slot = PCI_SLOT(dev->path.pci.devfn);
@@ -461,7 +461,7 @@
int __weak mainboard_get_spi_config(struct spi_config *cfg)
{
- printk(BIOS_SPEW, "%s/%s ( 0x%p )\n",
+ printk(BIOS_SPEW, "%s/%s (0x%p)\n",
__FILE__, __func__, (void *)cfg);
return -1;
}
@@ -475,7 +475,7 @@
uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS;
struct spi_config cfg;
- printk(BIOS_SPEW, "%s/%s ( 0x%p )\n",
+ printk(BIOS_SPEW, "%s/%s (0x%p)\n",
__FILE__, __func__, unused);
/* Set the lock enable on the BIOS control register. */
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index 6f0049f..8ce0a1d 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -37,8 +37,8 @@
* Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set.
* If either is true, then this is a warm reset so execute a Hard Reset
*/
- if ( (inb(0xcf9) == 0x04) ||
- (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE) ) {
+ if ((inb(0xcf9) == 0x04) ||
+ (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE)) {
outb(0x00, 0xcf9);
outb(0x06, 0xcf9);
}
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index c5863f4..13bc883 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -314,7 +314,7 @@
if (prev_sleep_state == ACPI_S3) {
/* S3 resume */
- if ( pFspInitParams->NvsBufferPtr == NULL) {
+ if (pFspInitParams->NvsBufferPtr == NULL) {
/* If waking from S3 and no cache then. */
printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
@@ -322,7 +322,7 @@
outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) &
~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
/* Reboot */
- printk(BIOS_WARNING,"Rebooting..\n" );
+ printk(BIOS_WARNING, "Rebooting..\n" );
system_reset();
/* Should not reach here.. */
die("Reboot System\n");
diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c
index 9f22b25..f909121 100644
--- a/src/soc/intel/fsp_baytrail/northcluster.c
+++ b/src/soc/intel/fsp_baytrail/northcluster.c
@@ -158,7 +158,7 @@
(bmbound - fsp_mem_base) >> 10);
if (highmem_size) {
- ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10 );
+ ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10);
}
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
highmem_size >> 20);
diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
index 7a25bfe..df2eb9c 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
@@ -589,9 +589,9 @@
}
} else if (hold < setup) {
- /* like this: (hold time != 0 )*/
+ /* like this: (hold time != 0)*/
/* xxxoooooooooooooooooo|ooooooooxxxxxxxxxxxxxxxxx */
- /* like this: (hold time == 0 ) */
+ /* like this: (hold time == 0) */
/* xxxoooooooooooooooxxx|xxxxxxxxxxxxxxxxxxxxxxxxx */
p->best_dqsdly = 0;
@@ -972,7 +972,7 @@
dqdqs_perbit_dly[i].best_last_dqsdly_pass = -2;
}
- /* 1. delay DQ ,find the pass widnow (left boundary)
+ /* 1. delay DQ,find the pass widnow (left boundary)
* 2. delay DQS find the pass window (right boundary)
* 3. find the best DQ / DQS to satify the middle value
* of the overall pass window per bit
@@ -1121,7 +1121,7 @@
dramc_dbg_msg("DQ Delay :\n");
for (i = 0; i < DATA_WIDTH_32BIT; i++) {
dramc_dbg_msg("DQ%d = %d ", i, dqdqs_perbit_dly[i].best_dqdly);
- if ( ((i + 1) % 4) == 0)
+ if (((i + 1) % 4) == 0)
dramc_dbg_msg("\n");
}
diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c
index c021303..872ed6c 100644
--- a/src/soc/mediatek/mt8173/emi.c
+++ b/src/soc/mediatek/mt8173/emi.c
@@ -138,19 +138,19 @@
if (value & CONA_DUAL_CH_EN)
bit_counter++;
- /* check if 32bit , 32 = 2^5*/
+ /* check if 32bit, 32 = 2^5*/
if (value & CONA_32BIT_EN)
bit_counter += 5;
else
bit_counter += 4;
/* check column address */
- /* 00 is 9 bits, 01 is 10 bits , 10 is 11 bits */
+ /* 00 is 9 bits, 01 is 10 bits, 10 is 11 bits */
bit_counter += ((value & COL_ADDR_BITS_MASK) >> COL_ADDR_BITS_SHIFT) +
9;
/* check if row address */
- /*00 is 13 bits , 01 is 14 bits , 10 is 15bits , 11 is 16 bits */
+ /*00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */
bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) +
13;
diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c
index 79ed316..31c77f5 100644
--- a/src/soc/mediatek/mt8173/gpio_init.c
+++ b/src/soc/mediatek/mt8173/gpio_init.c
@@ -58,7 +58,7 @@
}
/* other R/TDSEL */
- /* msdc2_ctrl5 , bit[3:0] = b`1010 */
+ /* msdc2_ctrl5, bit[3:0] = b`1010 */
write16(&mtk_gpio->msdc2_ctrl5.set, 0xA);
write16(&mtk_gpio->msdc2_ctrl5.rst, 0x5);
}
diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c
index 536ad31..5cc5889 100644
--- a/src/soc/nvidia/tegra124/sdram_lp0.c
+++ b/src/soc/nvidia/tegra124/sdram_lp0.c
@@ -44,9 +44,9 @@
#define pack(src, src_bits, dst, dst_bits) { \
_Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \
- (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \
+ (0 ? dst_bits), "byte range flipped (must be MSB:LSB)"); \
_Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \
- (0 ? dst_bits), "src and dst byte range lengths differ" ); \
+ (0 ? dst_bits), "src and dst byte range lengths differ"); \
u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \
dst &= ~(mask << (0 ? dst_bits)); \
dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \
diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c
index c3a4dd4..9eaf5f0 100644
--- a/src/soc/nvidia/tegra210/sdram_lp0.c
+++ b/src/soc/nvidia/tegra210/sdram_lp0.c
@@ -32,9 +32,9 @@
#define pack(src, src_bits, dst, dst_bits) { \
_Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \
- (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \
+ (0 ? dst_bits), "byte range flipped (must be MSB:LSB)"); \
_Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \
- (0 ? dst_bits), "src and dst byte range lengths differ" ); \
+ (0 ? dst_bits), "src and dst byte range lengths differ"); \
u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \
dst &= ~(mask << (0 ? dst_bits)); \
dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \
diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c
index 41056f8..662116e 100644
--- a/src/soc/rockchip/rk3288/gpio.c
+++ b/src/soc/rockchip/rk3288/gpio.c
@@ -47,7 +47,7 @@
{
if (is_pmu_gpio(gpio))
return &rk3288_pmu->gpio0pull[gpio.bank];
- /* There is one pmu gpio, gpio0 , so " - 1" */
+ /* There is one pmu gpio, gpio0, so " - 1" */
return &rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank];
}
diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c
index 63e30f6..a6cc3c7 100644
--- a/src/soc/samsung/exynos5250/clock.c
+++ b/src/soc/samsung/exynos5250/clock.c
@@ -617,7 +617,7 @@
epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
/*
- * Required period ( in cycles) to generate a stable clock output.
+ * Required period (in cycles) to generate a stable clock output.
* The maximum clock time can be up to 3000 * PDIV cycles of PLLs
* frequency input (as per spec)
*/
diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c
index 3c4bb04..04125d9 100644
--- a/src/soc/samsung/exynos5420/clock.c
+++ b/src/soc/samsung/exynos5420/clock.c
@@ -582,7 +582,7 @@
epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
/*
- * Required period ( in cycles) to generate a stable clock output.
+ * Required period (in cycles) to generate a stable clock output.
* The maximum clock time can be up to 3000 * PDIV cycles of PLLs
* frequency input (as per spec)
*/
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index a5f46be..75da9dd 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -96,7 +96,7 @@
for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index 1b6f5ae..30fcd37 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -45,8 +45,8 @@
#define BIT6 (1 << 6)
#define BIT7 (1 << 7)
-#define BIT8 (1 << 8 )
-#define BIT9 (1 << 9 )
+#define BIT8 (1 << 8)
+#define BIT9 (1 << 9)
#define BIT10 (1 << 10)
#define BIT11 (1 << 11)
#define BIT12 (1 << 12)
diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c
index ce0361a..33bc917 100644
--- a/src/southbridge/amd/agesa/hudson/smbus.c
+++ b/src/southbridge/amd/agesa/hudson/smbus.c
@@ -219,7 +219,7 @@
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc,
u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index 0948683..da7a1d8 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -168,17 +168,17 @@
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if (on) {
- pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
- outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
+ pm10_bar = (pci_read_config16(dev, 0x58) & 0xff00);
+ outl(((on << 1) + 0x10), (pm10_bar + 0x10));
inl(pm10_bar + 0x10);
on = 8-on;
printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
- (on*12)+(on>>1),(on&1)*5);
+ (on * 12) + (on >> 1), (on & 1) * 5);
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
pm_base = pci_read_config16(dev, 0x58) & 0xff00;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
+ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
#endif
}
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index aa323e4..d04646c 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -68,7 +68,7 @@
pci_write_config8(dev, 0x74, 4);
- /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
+ /* set VFSMAF (VID/FID System Management Action Field) to 2 */
pci_write_config32(dev, 0x70, 2<<12);
}
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c
index 52306ab..162a361 100644
--- a/src/southbridge/amd/amd8132/bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
@@ -213,7 +213,7 @@
if (chip_rev == 0x01) {
/* Errata #37 */
byte = pci_read_config8(dev, 0x0c);
- if (byte == 0x08 )
+ if (byte == 0x08)
pci_write_config8(dev, 0x0c, 0x10);
#if 0
@@ -272,7 +272,7 @@
/* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
dword = pci_read_config32(dev, 0xdc);
- dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE
+ dword |= (1<<1) | (1<<4); // stream disable 1 to 0, DBLINSRATE
dword |= (1<<18)|(1<<26);
dword &= ~((3<<16)|(3<<24));
pci_write_config32(dev, 0xdc, dword);
@@ -385,7 +385,7 @@
}
- if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
+ if ((chip_rev == 0x11) || (chip_rev == 0x12)) {
//for b1 b2
/* Errata #73 */
dword = pci_read_config32(dev, 0x80);
diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c
index 977ffb6..db87b6a 100644
--- a/src/southbridge/amd/cimx/sb800/fan.c
+++ b/src/southbridge/amd/cimx/sb800/fan.c
@@ -70,7 +70,7 @@
*
* Device 20, Function 3, Reg 0xA4
* [0]: if 1, the address specified in IMC_PortAddress is used.
- * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E )
+ * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E)
*/
pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01);
@@ -102,7 +102,7 @@
sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0;
message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone0_config_vals[i];
/* EC LDN9 function 83 zone 0 - Temperature Thresholds */
@@ -110,14 +110,14 @@
sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0;
sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone0_thresholds[i];
/*EC LDN9 function 85 zone 0 - Fan Speeds */
sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0;
message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];
}
@@ -133,7 +133,7 @@
sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1;
message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone1_config_vals[i];
/* EC LDN9 function 83 zone 1 - Temperature Thresholds */
@@ -141,14 +141,14 @@
sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1;
sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone1_thresholds[i];
/* EC LDN9 function 85 zone 1 - Fan Speeds */
sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1;
message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];
}
@@ -165,7 +165,7 @@
sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2;
message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone2_config_vals[i];
/* EC LDN9 function 83 zone 2 */
@@ -173,14 +173,14 @@
sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2;
sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone2_thresholds[i];
/* EC LDN9 function 85 zone 2 */
sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2;
message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];
}
@@ -197,7 +197,7 @@
sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3;
message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone3_config_vals[i];
/* EC LDN9 function 83 zone 3 */
@@ -205,14 +205,14 @@
sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3;
sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone3_thresholds[i];
/* EC LDN9 function 85 zone 3 */
sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3;
message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];
}
@@ -231,11 +231,11 @@
/* EC LDN9 function 89 TEMPIN channel 0 */
sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00;
- sb_config.Pecstruct.MSGFun89zone0MSGREG2 = ( sb_chip->imc_tempin0_at & 0xff);
+ sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG3 = ((sb_chip->imc_tempin0_at >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG4 = ((sb_chip->imc_tempin0_at >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG5 = ((sb_chip->imc_tempin0_at >> 24) & 0xff);
- sb_config.Pecstruct.MSGFun89zone0MSGREG6 = ( sb_chip->imc_tempin0_ct & 0xff);
+ sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG7 = ((sb_chip->imc_tempin0_ct >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG8 = ((sb_chip->imc_tempin0_ct >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG9 = ((sb_chip->imc_tempin0_ct >> 24) & 0xff);
@@ -249,11 +249,11 @@
/* EC LDN9 function 89 TEMPIN channel 1 */
sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01;
- sb_config.Pecstruct.MSGFun89zone1MSGREG2 = ( sb_chip->imc_tempin1_at & 0xff);
+ sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG3 = ((sb_chip->imc_tempin1_at >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG4 = ((sb_chip->imc_tempin1_at >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG5 = ((sb_chip->imc_tempin1_at >> 24) & 0xff);
- sb_config.Pecstruct.MSGFun89zone1MSGREG6 = ( sb_chip->imc_tempin1_ct & 0xff);
+ sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG7 = ((sb_chip->imc_tempin1_ct >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG8 = ((sb_chip->imc_tempin1_ct >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG9 = ((sb_chip->imc_tempin1_ct >> 24) & 0xff);
@@ -267,11 +267,11 @@
/* EC LDN9 function 89 TEMPIN channel 2 */
sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02;
- sb_config.Pecstruct.MSGFun89zone2MSGREG2 = ( sb_chip->imc_tempin2_at & 0xff);
+ sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG3 = ((sb_chip->imc_tempin2_at >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG4 = ((sb_chip->imc_tempin2_at >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG5 = ((sb_chip->imc_tempin2_at >> 24) & 0xff);
- sb_config.Pecstruct.MSGFun89zone2MSGREG6 = ( sb_chip->imc_tempin2_ct & 0xff);
+ sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG7 = ((sb_chip->imc_tempin2_ct >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG8 = ((sb_chip->imc_tempin2_ct >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG9 = ((sb_chip->imc_tempin2_ct >> 24) & 0xff);
@@ -285,11 +285,11 @@
/* EC LDN9 function 89 TEMPIN channel 3 */
sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03;
- sb_config.Pecstruct.MSGFun89zone3MSGREG2 = ( sb_chip->imc_tempin3_at & 0xff);
+ sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG3 = ((sb_chip->imc_tempin3_at >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG4 = ((sb_chip->imc_tempin3_at >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG5 = ((sb_chip->imc_tempin3_at >> 24) & 0xff);
- sb_config.Pecstruct.MSGFun89zone3MSGREG6 = ( sb_chip->imc_tempin3_ct & 0xff);
+ sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG7 = ((sb_chip->imc_tempin3_ct >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG8 = ((sb_chip->imc_tempin3_ct >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG9 = ((sb_chip->imc_tempin3_ct >> 24) & 0xff);
diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c
index 53b0a13..a4426ff 100644
--- a/src/southbridge/amd/cimx/sb800/smbus.c
+++ b/src/southbridge/amd/cimx/sb800/smbus.c
@@ -233,7 +233,7 @@
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c
index aaa0968..389aa8e 100644
--- a/src/southbridge/amd/cimx/sb900/smbus.c
+++ b/src/southbridge/amd/cimx/sb900/smbus.c
@@ -233,7 +233,7 @@
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index b5a86dc..47d20af 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -235,7 +235,7 @@
for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
diff --git a/src/southbridge/amd/pi/hudson/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c
index ce0361a..33bc917 100644
--- a/src/southbridge/amd/pi/hudson/smbus.c
+++ b/src/southbridge/amd/pi/hudson/smbus.c
@@ -219,7 +219,7 @@
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc,
u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index 865b577..017c764 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -35,7 +35,7 @@
static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data)
{
- pci_write_config32(dev, index_reg, index /* | 0x80 */ );
+ pci_write_config32(dev, index_reg, index /* | 0x80 */);
pci_write_config32(dev, index_reg + 0x4, data);
}
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 43bfb02..a765655 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -247,7 +247,7 @@
}
}
if (pMMIO[k].Limit != 0) {
- if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) {
+ if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) {
Base = 0;
}
else
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 6e072a6..a656921 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -816,7 +816,7 @@
for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
diff --git a/src/southbridge/amd/sb700/ramtop.c b/src/southbridge/amd/sb700/ramtop.c
index d306fff..4d26121 100644
--- a/src/southbridge/amd/sb700/ramtop.c
+++ b/src/southbridge/amd/sb700/ramtop.c
@@ -32,7 +32,7 @@
int nvram_pos = 0xfc, i;
for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
}
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 1d1ac13..975e5ac 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -461,7 +461,7 @@
else
printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
(i / 2) ? "Secondary" : "Primary",
- (i % 2 ) ? "Slave" : "Master",
+ (i % 2) ? "Slave" : "Master",
(j == 10) ? "not " : "",
(j == 10) ? j : j + 1);
} else {
@@ -470,7 +470,7 @@
else
printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
(i / 2) ? "Secondary" : "Primary",
- (i % 2 ) ? "Slave" : "Master", i);
+ (i % 2) ? "Slave" : "Master", i);
}
}
@@ -510,7 +510,7 @@
write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
- /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+ /* ????? why CIM does not set the AcpiGpe0BlkAddr, but use it??? */
/* word = 0x0000; */
/* word = pm_ioread(0x28); */
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index d73b75d..2ace992 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -633,7 +633,7 @@
for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index 15b2527..2186d37 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -177,7 +177,7 @@
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
- if ( byte == 0x1 ) {
+ if (byte == 0x1) {
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
/* Try to do something about it. */
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
@@ -212,13 +212,13 @@
}
printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
(i / 2) ? "Secondary" : "Primary",
- (i % 2 ) ? "Slave" : "Master",
+ (i % 2) ? "Slave" : "Master",
(j == 10) ? "not " : "",
(j == 10) ? j : j + 1);
} else {
printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
(i / 2) ? "Secondary" : "Primary",
- (i % 2 ) ? "Slave" : "Master", i);
+ (i % 2) ? "Slave" : "Master", i);
}
}
@@ -237,7 +237,7 @@
write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
- /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+ /* ????? why CIM does not set the AcpiGpe0BlkAddr, but use it??? */
/* word = 0x0000; */
/* word = pm_ioread(0x28); */
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index d4ed3cc..fdb6283 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -45,8 +45,8 @@
#define BIT6 (1 << 6)
#define BIT7 (1 << 7)
-#define BIT8 (1 << 8 )
-#define BIT9 (1 << 9 )
+#define BIT8 (1 << 8)
+#define BIT9 (1 << 9)
#define BIT10 (1 << 10)
#define BIT11 (1 << 11)
#define BIT12 (1 << 12)
diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c
index 89244f4..aa4133b 100644
--- a/src/southbridge/amd/sb800/smbus.c
+++ b/src/southbridge/amd/sb800/smbus.c
@@ -222,7 +222,7 @@
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc,
u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 8986e67..159f3e4 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -665,7 +665,7 @@
/* CIMx CommonPortInit settings that are not set above. */
pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */
- if ( port == 8 )
+ if (port == 8)
set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23);
#if 0 //SR56x0 pcie Gen2 code is not tested yet, we should enable it again when test finished.
@@ -687,7 +687,7 @@
pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3);
/* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */
- if ( port != 8)
+ if (port != 8)
set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2);
/* Not sure about this PME setup */
@@ -806,7 +806,7 @@
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6);
/* Step 20: Disables immediate RCB timeout on link down */
- if (!((pci_read_config32(dev, 0x6C ) >> 6) & 0x01)) {
+ if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) {
set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
}
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index 8df4a00..d4ff783 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -35,7 +35,7 @@
/* Activate PMBAR. */
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
/* Unlock registers. */
outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN,
diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c
index f9f3134..1e281aa 100644
--- a/src/southbridge/intel/fsp_bd82x6x/early_init.c
+++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c
@@ -142,7 +142,7 @@
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
printk(BIOS_DEBUG, " done.\n");
diff --git a/src/southbridge/intel/fsp_i89xx/early_init.c b/src/southbridge/intel/fsp_i89xx/early_init.c
index 7ce3c7f..af79925 100644
--- a/src/southbridge/intel/fsp_i89xx/early_init.c
+++ b/src/southbridge/intel/fsp_i89xx/early_init.c
@@ -29,7 +29,7 @@
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
printk(BIOS_DEBUG, " done.\n");
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index 268ea66..863ff6a 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -172,7 +172,7 @@
/* For reference print FSP version */
uint32_t version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "FSP Version %d.%d.%d Build %d\n",
- version >> 24 , (version >> 16) & 0xff,
+ version >> 24, (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (uint32_t)status);
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 3477c52..5b95c57 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -68,7 +68,7 @@
* power-on default is 0x7fffbfffh */
if (gpo) {
/* only 8bit access allowed */
- outb( gpo & 0xff, DEFAULT_PMBASE + GPO0);
+ outb(gpo & 0xff, DEFAULT_PMBASE + GPO0);
outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1);
outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2);
outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3);
diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index 30b68ec..180f41a 100644
--- a/src/southbridge/nvidia/ck804/early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
@@ -255,7 +255,7 @@
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
- RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23),
+ RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23),
#endif
#if IS_ENABLED(CONFIG_CK804_USE_ACI)
diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index 6ddd59e..5289146 100644
--- a/src/southbridge/nvidia/mcp55/early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
@@ -86,7 +86,7 @@
for (j = 0; j < mcp55_num; j++) {
setup_resource_map_offset(ctrl_devport_conf,
ARRAY_SIZE(ctrl_devport_conf),
- PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
+ PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
}
@@ -103,7 +103,7 @@
for (j = 0; j < mcp55_num; j++) {
setup_resource_map_offset(ctrl_devport_conf_clear,
ARRAY_SIZE(ctrl_devport_conf_clear),
- PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
+ PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
}
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index bdbcba7..786a510 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -166,7 +166,7 @@
/* For CF socket we need an extra memory window for
* the control structure of the CF itself
*/
- if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
+ if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)) {
/* fake index as it isn't in PCI config space */
resource = new_resource(dev, 1);
resource->flags |= IORESOURCE_MEM;
@@ -181,9 +181,9 @@
{
struct resource *resource;
printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));
- if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
+ if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)) {
resource = find_resource(dev,1);
- if ( !(resource->flags & IORESOURCE_STORED) ){
+ if (!(resource->flags & IORESOURCE_STORED)) {
resource->flags |= IORESOURCE_STORED;
printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base);
cf_base = resource->base;
diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c
index acd2ab4..82438e4 100644
--- a/src/superio/serverengines/pilot/early_init.c
+++ b/src/superio/serverengines/pilot/early_init.c
@@ -59,7 +59,7 @@
pnp_set_logical_device(PNP_DEV(port, 0x4));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
- pnp_set_enable( PNP_DEV(port, 0x4), 0);
+ pnp_set_enable(PNP_DEV(port, 0x4), 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c
index eea9dce..0ebd207 100644
--- a/src/superio/smsc/sch4037/sch4037_early_init.c
+++ b/src/superio/smsc/sch4037/sch4037_early_init.c
@@ -41,7 +41,7 @@
/* Auto power management */
pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
- pnp_write_config(dev, 0x23, 0 );
+ pnp_write_config(dev, 0x23, 0);
/* Enable SMSC UART 0 */
dev = PNP_DEV(port, SMSCSUPERIO_SP1);