Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 1 | // 16bit code to handle system clocks. |
| 2 | // |
Kevin O'Connor | abf31d3 | 2010-07-26 22:33:54 -0400 | [diff] [blame] | 3 | // Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 4 | // Copyright (C) 2002 MandrakeSoft S.A. |
| 5 | // |
Kevin O'Connor | b1b7c2a | 2009-01-15 20:52:58 -0500 | [diff] [blame] | 6 | // This file may be distributed under the terms of the GNU LGPLv3 license. |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 7 | |
Kevin O'Connor | 9521e26 | 2008-07-04 13:04:29 -0400 | [diff] [blame] | 8 | #include "biosvar.h" // SET_BDA |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 9 | #include "util.h" // debug_enter |
| 10 | #include "disk.h" // floppy_tick |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 11 | #include "cmos.h" // inb_cmos |
Kevin O'Connor | d21c089 | 2008-11-26 17:02:43 -0500 | [diff] [blame] | 12 | #include "pic.h" // eoi_pic1 |
Kevin O'Connor | 9521e26 | 2008-07-04 13:04:29 -0400 | [diff] [blame] | 13 | #include "bregs.h" // struct bregs |
Kevin O'Connor | 15157a3 | 2008-12-13 11:10:37 -0500 | [diff] [blame] | 14 | #include "biosvar.h" // GET_GLOBAL |
Kevin O'Connor | 0e88576 | 2010-05-01 22:14:40 -0400 | [diff] [blame] | 15 | #include "usb-hid.h" // usb_check_event |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 16 | |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 17 | // RTC register flags |
| 18 | #define RTC_A_UIP 0x80 |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 19 | |
| 20 | #define RTC_B_SET 0x80 |
| 21 | #define RTC_B_PIE 0x40 |
| 22 | #define RTC_B_AIE 0x20 |
| 23 | #define RTC_B_UIE 0x10 |
| 24 | #define RTC_B_BIN 0x04 |
| 25 | #define RTC_B_24HR 0x02 |
| 26 | #define RTC_B_DSE 0x01 |
| 27 | |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 28 | |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 29 | // Bits for PORT_PS2_CTRLB |
| 30 | #define PPCB_T2GATE (1<<0) |
| 31 | #define PPCB_SPKR (1<<1) |
| 32 | #define PPCB_T2OUT (1<<5) |
| 33 | |
| 34 | // Bits for PORT_PIT_MODE |
| 35 | #define PM_SEL_TIMER0 (0<<6) |
| 36 | #define PM_SEL_TIMER1 (1<<6) |
| 37 | #define PM_SEL_TIMER2 (2<<6) |
| 38 | #define PM_SEL_READBACK (3<<6) |
| 39 | #define PM_ACCESS_LATCH (0<<4) |
| 40 | #define PM_ACCESS_LOBYTE (1<<4) |
| 41 | #define PM_ACCESS_HIBYTE (2<<4) |
| 42 | #define PM_ACCESS_WORD (3<<4) |
| 43 | #define PM_MODE0 (0<<1) |
| 44 | #define PM_MODE1 (1<<1) |
| 45 | #define PM_MODE2 (2<<1) |
| 46 | #define PM_MODE3 (3<<1) |
| 47 | #define PM_MODE4 (4<<1) |
| 48 | #define PM_MODE5 (5<<1) |
| 49 | #define PM_CNT_BINARY (0<<0) |
| 50 | #define PM_CNT_BCD (1<<0) |
Kevin O'Connor | 745de85 | 2012-01-29 14:15:14 -0500 | [diff] [blame^] | 51 | #define PM_READ_COUNTER0 (1<<1) |
| 52 | #define PM_READ_COUNTER1 (1<<2) |
| 53 | #define PM_READ_COUNTER2 (1<<3) |
| 54 | #define PM_READ_STATUSVALUE (0<<4) |
| 55 | #define PM_READ_VALUE (1<<4) |
| 56 | #define PM_READ_STATUS (2<<4) |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 57 | |
| 58 | |
| 59 | /**************************************************************** |
| 60 | * TSC timer |
| 61 | ****************************************************************/ |
| 62 | |
Kevin O'Connor | 6aee52d | 2009-09-27 20:07:40 -0400 | [diff] [blame] | 63 | #define CALIBRATE_COUNT 0x800 // Approx 1.7ms |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 64 | |
Kevin O'Connor | 372e071 | 2009-09-09 09:51:31 -0400 | [diff] [blame] | 65 | u32 cpu_khz VAR16VISIBLE; |
Kevin O'Connor | 745de85 | 2012-01-29 14:15:14 -0500 | [diff] [blame^] | 66 | u8 no_tsc VAR16VISIBLE; |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 67 | |
| 68 | static void |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 69 | calibrate_tsc(void) |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 70 | { |
Kevin O'Connor | 745de85 | 2012-01-29 14:15:14 -0500 | [diff] [blame^] | 71 | u32 eax, ebx, ecx, edx, cpuid_features = 0; |
| 72 | cpuid(0, &eax, &ebx, &ecx, &edx); |
| 73 | if (eax > 0) |
| 74 | cpuid(1, &eax, &ebx, &ecx, &cpuid_features); |
| 75 | |
| 76 | if (!(cpuid_features & CPUID_TSC)) { |
| 77 | SET_GLOBAL(no_tsc, 1); |
| 78 | SET_GLOBAL(cpu_khz, PIT_TICK_RATE / 1000); |
| 79 | dprintf(3, "386/486 class CPU. Using TSC emulation\n"); |
| 80 | return; |
| 81 | } |
| 82 | |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 83 | // Setup "timer2" |
| 84 | u8 orig = inb(PORT_PS2_CTRLB); |
| 85 | outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB); |
| 86 | /* binary, mode 0, LSB/MSB, Ch 2 */ |
| 87 | outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE); |
| 88 | /* LSB of ticks */ |
| 89 | outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2); |
| 90 | /* MSB of ticks */ |
| 91 | outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2); |
| 92 | |
| 93 | u64 start = rdtscll(); |
| 94 | while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0) |
| 95 | ; |
| 96 | u64 end = rdtscll(); |
| 97 | |
| 98 | // Restore PORT_PS2_CTRLB |
| 99 | outb(orig, PORT_PS2_CTRLB); |
| 100 | |
| 101 | // Store calibrated cpu khz. |
| 102 | u64 diff = end - start; |
| 103 | dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n" |
| 104 | , (u32)start, (u32)end, (u32)diff); |
| 105 | u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT; |
Kevin O'Connor | 15157a3 | 2008-12-13 11:10:37 -0500 | [diff] [blame] | 106 | SET_GLOBAL(cpu_khz, hz / 1000); |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 107 | |
| 108 | dprintf(1, "CPU Mhz=%u\n", hz / 1000000); |
| 109 | } |
| 110 | |
Kevin O'Connor | 745de85 | 2012-01-29 14:15:14 -0500 | [diff] [blame^] | 111 | static u64 |
| 112 | emulate_tsc(void) |
| 113 | { |
| 114 | int cnt, d; |
| 115 | u16 ebda_seg = get_ebda_seg(); |
| 116 | u64 ret; |
| 117 | /* read timer 0 current count */ |
| 118 | ret = GET_EBDA2(ebda_seg, tsc_8254); |
| 119 | /* readback mode has slightly shifted registers, works on all 8254, readback PIT0 latch */ |
| 120 | outb(PM_SEL_READBACK | PM_READ_VALUE | PM_READ_COUNTER0, PORT_PIT_MODE); |
| 121 | cnt = (inb(PORT_PIT_COUNTER0) | (inb(PORT_PIT_COUNTER0) << 8)); |
| 122 | d = GET_EBDA2(ebda_seg, last_tsc_8254) - cnt; |
| 123 | /* Determine the ticks count from last invocation of this function */ |
| 124 | ret += (d > 0) ? d : (PIT_TICK_INTERVAL + d); |
| 125 | SET_EBDA2(ebda_seg, last_tsc_8254, cnt); |
| 126 | SET_EBDA2(ebda_seg, tsc_8254, ret); |
| 127 | return ret; |
| 128 | } |
| 129 | |
| 130 | static u64 |
| 131 | get_tsc(void) |
| 132 | { |
| 133 | if (unlikely(GET_GLOBAL(no_tsc))) |
| 134 | return emulate_tsc(); |
| 135 | return rdtscll(); |
| 136 | } |
| 137 | |
| 138 | int |
| 139 | check_tsc(u64 end) |
| 140 | { |
| 141 | return (s64)(get_tsc() - end) > 0; |
| 142 | } |
| 143 | |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 144 | static void |
Kevin O'Connor | 89eb624 | 2009-10-22 22:30:37 -0400 | [diff] [blame] | 145 | tscdelay(u64 diff) |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 146 | { |
Kevin O'Connor | 745de85 | 2012-01-29 14:15:14 -0500 | [diff] [blame^] | 147 | u64 start = get_tsc(); |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 148 | u64 end = start + diff; |
Kevin O'Connor | 144817b | 2010-05-23 10:46:49 -0400 | [diff] [blame] | 149 | while (!check_tsc(end)) |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 150 | cpu_relax(); |
| 151 | } |
| 152 | |
Kevin O'Connor | 10ad799 | 2009-10-24 11:06:08 -0400 | [diff] [blame] | 153 | static void |
| 154 | tscsleep(u64 diff) |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 155 | { |
Kevin O'Connor | 745de85 | 2012-01-29 14:15:14 -0500 | [diff] [blame^] | 156 | u64 start = get_tsc(); |
Kevin O'Connor | 10ad799 | 2009-10-24 11:06:08 -0400 | [diff] [blame] | 157 | u64 end = start + diff; |
Kevin O'Connor | 144817b | 2010-05-23 10:46:49 -0400 | [diff] [blame] | 158 | while (!check_tsc(end)) |
Kevin O'Connor | 10ad799 | 2009-10-24 11:06:08 -0400 | [diff] [blame] | 159 | yield(); |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 160 | } |
Kevin O'Connor | 10ad799 | 2009-10-24 11:06:08 -0400 | [diff] [blame] | 161 | |
| 162 | void ndelay(u32 count) { |
| 163 | tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000); |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 164 | } |
Kevin O'Connor | 10ad799 | 2009-10-24 11:06:08 -0400 | [diff] [blame] | 165 | void udelay(u32 count) { |
| 166 | tscdelay(count * GET_GLOBAL(cpu_khz) / 1000); |
| 167 | } |
| 168 | void mdelay(u32 count) { |
| 169 | tscdelay(count * GET_GLOBAL(cpu_khz)); |
| 170 | } |
| 171 | |
| 172 | void nsleep(u32 count) { |
| 173 | tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000); |
| 174 | } |
| 175 | void usleep(u32 count) { |
| 176 | tscsleep(count * GET_GLOBAL(cpu_khz) / 1000); |
| 177 | } |
| 178 | void msleep(u32 count) { |
| 179 | tscsleep(count * GET_GLOBAL(cpu_khz)); |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 180 | } |
| 181 | |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 182 | // Return the TSC value that is 'msecs' time in the future. |
| 183 | u64 |
| 184 | calc_future_tsc(u32 msecs) |
| 185 | { |
Kevin O'Connor | 15157a3 | 2008-12-13 11:10:37 -0500 | [diff] [blame] | 186 | u32 khz = GET_GLOBAL(cpu_khz); |
Kevin O'Connor | 745de85 | 2012-01-29 14:15:14 -0500 | [diff] [blame^] | 187 | return get_tsc() + ((u64)khz * msecs); |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 188 | } |
Kevin O'Connor | 1c46a54 | 2009-10-17 23:53:32 -0400 | [diff] [blame] | 189 | u64 |
| 190 | calc_future_tsc_usec(u32 usecs) |
| 191 | { |
| 192 | u32 khz = GET_GLOBAL(cpu_khz); |
Kevin O'Connor | 745de85 | 2012-01-29 14:15:14 -0500 | [diff] [blame^] | 193 | return get_tsc() + ((u64)(khz/1000) * usecs); |
Kevin O'Connor | 1c46a54 | 2009-10-17 23:53:32 -0400 | [diff] [blame] | 194 | } |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 195 | |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 196 | |
| 197 | /**************************************************************** |
| 198 | * Init |
| 199 | ****************************************************************/ |
| 200 | |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 201 | static int |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 202 | rtc_updating(void) |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 203 | { |
| 204 | // This function checks to see if the update-in-progress bit |
| 205 | // is set in CMOS Status Register A. If not, it returns 0. |
| 206 | // If it is set, it tries to wait until there is a transition |
| 207 | // to 0, and will return 0 if such a transition occurs. A -1 |
| 208 | // is returned only after timing out. The maximum period |
Kevin O'Connor | 4f5586c | 2009-02-16 10:14:10 -0500 | [diff] [blame] | 209 | // that this bit should be set is constrained to (1984+244) |
Kevin O'Connor | 11cc662 | 2010-03-13 23:04:41 -0500 | [diff] [blame] | 210 | // useconds, but we wait for longer just to be sure. |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 211 | |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 212 | if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0) |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 213 | return 0; |
Kevin O'Connor | 11cc662 | 2010-03-13 23:04:41 -0500 | [diff] [blame] | 214 | u64 end = calc_future_tsc(15); |
| 215 | for (;;) { |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 216 | if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0) |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 217 | return 0; |
Kevin O'Connor | 144817b | 2010-05-23 10:46:49 -0400 | [diff] [blame] | 218 | if (check_tsc(end)) |
Kevin O'Connor | 11cc662 | 2010-03-13 23:04:41 -0500 | [diff] [blame] | 219 | // update-in-progress never transitioned to 0 |
| 220 | return -1; |
| 221 | yield(); |
| 222 | } |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 223 | } |
| 224 | |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 225 | static void |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 226 | pit_setup(void) |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 227 | { |
| 228 | // timer0: binary count, 16bit count, mode 2 |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 229 | outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE); |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 230 | // maximum count of 0000H = 18.2Hz |
| 231 | outb(0x0, PORT_PIT_COUNTER0); |
| 232 | outb(0x0, PORT_PIT_COUNTER0); |
| 233 | } |
| 234 | |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 235 | static void |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 236 | init_rtc(void) |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 237 | { |
Kevin O'Connor | 4f5586c | 2009-02-16 10:14:10 -0500 | [diff] [blame] | 238 | outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 239 | u8 regB = inb_cmos(CMOS_STATUS_B); |
| 240 | outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B); |
| 241 | inb_cmos(CMOS_STATUS_C); |
| 242 | inb_cmos(CMOS_STATUS_D); |
| 243 | } |
| 244 | |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 245 | static u32 |
| 246 | bcd2bin(u8 val) |
| 247 | { |
| 248 | return (val & 0xf) + ((val >> 4) * 10); |
| 249 | } |
| 250 | |
| 251 | void |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 252 | timer_setup(void) |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 253 | { |
Kevin O'Connor | 35192dd | 2008-06-08 19:18:33 -0400 | [diff] [blame] | 254 | dprintf(3, "init timer\n"); |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 255 | calibrate_tsc(); |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 256 | pit_setup(); |
| 257 | |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 258 | init_rtc(); |
Kevin O'Connor | 4e6c970 | 2008-12-13 10:45:50 -0500 | [diff] [blame] | 259 | rtc_updating(); |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 260 | u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS)); |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 261 | u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES)); |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 262 | u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS)); |
Kevin O'Connor | 6aee52d | 2009-09-27 20:07:40 -0400 | [diff] [blame] | 263 | u32 ticks = (hours * 60 + minutes) * 60 + seconds; |
| 264 | ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL; |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 265 | SET_BDA(timer_counter, ticks); |
Kevin O'Connor | f54c150 | 2008-06-14 15:56:16 -0400 | [diff] [blame] | 266 | |
Kevin O'Connor | cc9e1bf | 2010-07-28 21:31:38 -0400 | [diff] [blame] | 267 | enable_hwirq(0, FUNC16(entry_08)); |
| 268 | enable_hwirq(8, FUNC16(entry_70)); |
Kevin O'Connor | e6eb3f5 | 2008-04-13 17:37:41 -0400 | [diff] [blame] | 269 | } |
| 270 | |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 271 | |
| 272 | /**************************************************************** |
| 273 | * Standard clock functions |
| 274 | ****************************************************************/ |
| 275 | |
Kevin O'Connor | b5cc2ca | 2010-05-23 11:38:53 -0400 | [diff] [blame] | 276 | #define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL) |
| 277 | |
| 278 | // Calculate the timer value at 'count' number of full timer ticks in |
| 279 | // the future. |
| 280 | u32 |
| 281 | calc_future_timer_ticks(u32 count) |
| 282 | { |
| 283 | return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY; |
| 284 | } |
Kevin O'Connor | bb68591 | 2010-05-23 12:40:40 -0400 | [diff] [blame] | 285 | |
Kevin O'Connor | b5cc2ca | 2010-05-23 11:38:53 -0400 | [diff] [blame] | 286 | // Return the timer value that is 'msecs' time in the future. |
| 287 | u32 |
| 288 | calc_future_timer(u32 msecs) |
| 289 | { |
Kevin O'Connor | bb68591 | 2010-05-23 12:40:40 -0400 | [diff] [blame] | 290 | if (!msecs) |
| 291 | return GET_BDA(timer_counter); |
Kevin O'Connor | abf31d3 | 2010-07-26 22:33:54 -0400 | [diff] [blame] | 292 | u32 kticks = DIV_ROUND_UP((u64)msecs * PIT_TICK_RATE, PIT_TICK_INTERVAL); |
Kevin O'Connor | b5cc2ca | 2010-05-23 11:38:53 -0400 | [diff] [blame] | 293 | u32 ticks = DIV_ROUND_UP(kticks, 1000); |
| 294 | return calc_future_timer_ticks(ticks); |
| 295 | } |
Kevin O'Connor | bb68591 | 2010-05-23 12:40:40 -0400 | [diff] [blame] | 296 | |
Kevin O'Connor | b5cc2ca | 2010-05-23 11:38:53 -0400 | [diff] [blame] | 297 | // Check if the given timer value has passed. |
| 298 | int |
| 299 | check_timer(u32 end) |
| 300 | { |
| 301 | return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY) |
| 302 | < (TICKS_PER_DAY/2)); |
| 303 | } |
| 304 | |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 305 | // get current clock count |
| 306 | static void |
| 307 | handle_1a00(struct bregs *regs) |
| 308 | { |
Kevin O'Connor | 68c5139 | 2010-03-13 22:23:44 -0500 | [diff] [blame] | 309 | yield(); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 310 | u32 ticks = GET_BDA(timer_counter); |
| 311 | regs->cx = ticks >> 16; |
| 312 | regs->dx = ticks; |
| 313 | regs->al = GET_BDA(timer_rollover); |
| 314 | SET_BDA(timer_rollover, 0); // reset flag |
Kevin O'Connor | 6c78122 | 2008-03-09 12:19:23 -0400 | [diff] [blame] | 315 | set_success(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | // Set Current Clock Count |
| 319 | static void |
| 320 | handle_1a01(struct bregs *regs) |
| 321 | { |
| 322 | u32 ticks = (regs->cx << 16) | regs->dx; |
| 323 | SET_BDA(timer_counter, ticks); |
| 324 | SET_BDA(timer_rollover, 0); // reset flag |
Kevin O'Connor | 15157a3 | 2008-12-13 11:10:37 -0500 | [diff] [blame] | 325 | // XXX - should use set_code_success()? |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 326 | regs->ah = 0; |
Kevin O'Connor | 6c78122 | 2008-03-09 12:19:23 -0400 | [diff] [blame] | 327 | set_success(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 328 | } |
| 329 | |
| 330 | // Read CMOS Time |
| 331 | static void |
| 332 | handle_1a02(struct bregs *regs) |
| 333 | { |
| 334 | if (rtc_updating()) { |
Kevin O'Connor | dfefeb5 | 2009-12-13 13:04:17 -0500 | [diff] [blame] | 335 | set_invalid(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 336 | return; |
| 337 | } |
| 338 | |
| 339 | regs->dh = inb_cmos(CMOS_RTC_SECONDS); |
| 340 | regs->cl = inb_cmos(CMOS_RTC_MINUTES); |
| 341 | regs->ch = inb_cmos(CMOS_RTC_HOURS); |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 342 | regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE; |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 343 | regs->ah = 0; |
| 344 | regs->al = regs->ch; |
Kevin O'Connor | 6c78122 | 2008-03-09 12:19:23 -0400 | [diff] [blame] | 345 | set_success(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | // Set CMOS Time |
| 349 | static void |
| 350 | handle_1a03(struct bregs *regs) |
| 351 | { |
| 352 | // Using a debugger, I notice the following masking/setting |
| 353 | // of bits in Status Register B, by setting Reg B to |
| 354 | // a few values and getting its value after INT 1A was called. |
| 355 | // |
| 356 | // try#1 try#2 try#3 |
| 357 | // before 1111 1101 0111 1101 0000 0000 |
| 358 | // after 0110 0010 0110 0010 0000 0010 |
| 359 | // |
| 360 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1 |
| 361 | // My assumption: RegB = ((RegB & 01100000b) | 00000010b) |
| 362 | if (rtc_updating()) { |
| 363 | init_rtc(); |
| 364 | // fall through as if an update were not in progress |
| 365 | } |
| 366 | outb_cmos(regs->dh, CMOS_RTC_SECONDS); |
| 367 | outb_cmos(regs->cl, CMOS_RTC_MINUTES); |
| 368 | outb_cmos(regs->ch, CMOS_RTC_HOURS); |
| 369 | // Set Daylight Savings time enabled bit to requested value |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 370 | u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE)) |
| 371 | | RTC_B_24HR | (regs->dl & RTC_B_DSE)); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 372 | outb_cmos(val8, CMOS_STATUS_B); |
| 373 | regs->ah = 0; |
| 374 | regs->al = val8; // val last written to Reg B |
Kevin O'Connor | 6c78122 | 2008-03-09 12:19:23 -0400 | [diff] [blame] | 375 | set_success(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 376 | } |
| 377 | |
| 378 | // Read CMOS Date |
| 379 | static void |
| 380 | handle_1a04(struct bregs *regs) |
| 381 | { |
| 382 | regs->ah = 0; |
| 383 | if (rtc_updating()) { |
Kevin O'Connor | dfefeb5 | 2009-12-13 13:04:17 -0500 | [diff] [blame] | 384 | set_invalid(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 385 | return; |
| 386 | } |
| 387 | regs->cl = inb_cmos(CMOS_RTC_YEAR); |
| 388 | regs->dh = inb_cmos(CMOS_RTC_MONTH); |
| 389 | regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH); |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 390 | if (CONFIG_COREBOOT) { |
| 391 | if (regs->cl > 0x80) |
| 392 | regs->ch = 0x19; |
| 393 | else |
| 394 | regs->ch = 0x20; |
| 395 | } else { |
| 396 | regs->ch = inb_cmos(CMOS_CENTURY); |
| 397 | } |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 398 | regs->al = regs->ch; |
Kevin O'Connor | 6c78122 | 2008-03-09 12:19:23 -0400 | [diff] [blame] | 399 | set_success(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 400 | } |
| 401 | |
| 402 | // Set CMOS Date |
| 403 | static void |
| 404 | handle_1a05(struct bregs *regs) |
| 405 | { |
| 406 | // Using a debugger, I notice the following masking/setting |
| 407 | // of bits in Status Register B, by setting Reg B to |
| 408 | // a few values and getting its value after INT 1A was called. |
| 409 | // |
| 410 | // try#1 try#2 try#3 try#4 |
| 411 | // before 1111 1101 0111 1101 0000 0010 0000 0000 |
| 412 | // after 0110 1101 0111 1101 0000 0010 0000 0000 |
| 413 | // |
| 414 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1 |
| 415 | // My assumption: RegB = (RegB & 01111111b) |
| 416 | if (rtc_updating()) { |
| 417 | init_rtc(); |
Kevin O'Connor | dfefeb5 | 2009-12-13 13:04:17 -0500 | [diff] [blame] | 418 | set_invalid(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 419 | return; |
| 420 | } |
| 421 | outb_cmos(regs->cl, CMOS_RTC_YEAR); |
| 422 | outb_cmos(regs->dh, CMOS_RTC_MONTH); |
| 423 | outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH); |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 424 | if (!CONFIG_COREBOOT) |
| 425 | outb_cmos(regs->ch, CMOS_CENTURY); |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 426 | // clear halt-clock bit |
| 427 | u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET; |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 428 | outb_cmos(val8, CMOS_STATUS_B); |
| 429 | regs->ah = 0; |
| 430 | regs->al = val8; // AL = val last written to Reg B |
Kevin O'Connor | 6c78122 | 2008-03-09 12:19:23 -0400 | [diff] [blame] | 431 | set_success(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | // Set Alarm Time in CMOS |
| 435 | static void |
| 436 | handle_1a06(struct bregs *regs) |
| 437 | { |
| 438 | // Using a debugger, I notice the following masking/setting |
| 439 | // of bits in Status Register B, by setting Reg B to |
| 440 | // a few values and getting its value after INT 1A was called. |
| 441 | // |
| 442 | // try#1 try#2 try#3 |
| 443 | // before 1101 1111 0101 1111 0000 0000 |
| 444 | // after 0110 1111 0111 1111 0010 0000 |
| 445 | // |
| 446 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1 |
| 447 | // My assumption: RegB = ((RegB & 01111111b) | 00100000b) |
| 448 | u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B |
| 449 | regs->ax = 0; |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 450 | if (val8 & RTC_B_AIE) { |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 451 | // Alarm interrupt enabled already |
Kevin O'Connor | dfefeb5 | 2009-12-13 13:04:17 -0500 | [diff] [blame] | 452 | set_invalid(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 453 | return; |
| 454 | } |
| 455 | if (rtc_updating()) { |
| 456 | init_rtc(); |
| 457 | // fall through as if an update were not in progress |
| 458 | } |
| 459 | outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM); |
| 460 | outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM); |
| 461 | outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 462 | // enable Status Reg B alarm bit, clear halt clock bit |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 463 | outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B); |
Kevin O'Connor | 6c78122 | 2008-03-09 12:19:23 -0400 | [diff] [blame] | 464 | set_success(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 465 | } |
| 466 | |
| 467 | // Turn off Alarm |
| 468 | static void |
| 469 | handle_1a07(struct bregs *regs) |
| 470 | { |
| 471 | // Using a debugger, I notice the following masking/setting |
| 472 | // of bits in Status Register B, by setting Reg B to |
| 473 | // a few values and getting its value after INT 1A was called. |
| 474 | // |
| 475 | // try#1 try#2 try#3 try#4 |
| 476 | // before 1111 1101 0111 1101 0010 0000 0010 0010 |
| 477 | // after 0100 0101 0101 0101 0000 0000 0000 0010 |
| 478 | // |
| 479 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1 |
| 480 | // My assumption: RegB = (RegB & 01010111b) |
| 481 | u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B |
| 482 | // clear clock-halt bit, disable alarm bit |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 483 | outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 484 | regs->ah = 0; |
| 485 | regs->al = val8; // val last written to Reg B |
Kevin O'Connor | 6c78122 | 2008-03-09 12:19:23 -0400 | [diff] [blame] | 486 | set_success(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 487 | } |
| 488 | |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 489 | // Unsupported |
| 490 | static void |
| 491 | handle_1aXX(struct bregs *regs) |
| 492 | { |
Kevin O'Connor | dfefeb5 | 2009-12-13 13:04:17 -0500 | [diff] [blame] | 493 | set_unimplemented(regs); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 494 | } |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 495 | |
| 496 | // INT 1Ah Time-of-day Service Entry Point |
Kevin O'Connor | 1978676 | 2008-03-05 21:09:59 -0500 | [diff] [blame] | 497 | void VISIBLE16 |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 498 | handle_1a(struct bregs *regs) |
| 499 | { |
Kevin O'Connor | 15c1f22 | 2008-06-12 22:59:43 -0400 | [diff] [blame] | 500 | debug_enter(regs, DEBUG_HDL_1a); |
Kevin O'Connor | 4b60c00 | 2008-02-25 22:29:55 -0500 | [diff] [blame] | 501 | switch (regs->ah) { |
| 502 | case 0x00: handle_1a00(regs); break; |
| 503 | case 0x01: handle_1a01(regs); break; |
| 504 | case 0x02: handle_1a02(regs); break; |
| 505 | case 0x03: handle_1a03(regs); break; |
| 506 | case 0x04: handle_1a04(regs); break; |
| 507 | case 0x05: handle_1a05(regs); break; |
| 508 | case 0x06: handle_1a06(regs); break; |
| 509 | case 0x07: handle_1a07(regs); break; |
| 510 | case 0xb1: handle_1ab1(regs); break; |
| 511 | default: handle_1aXX(regs); break; |
| 512 | } |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 513 | } |
| 514 | |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 515 | // INT 08h System Timer ISR Entry Point |
Kevin O'Connor | 1978676 | 2008-03-05 21:09:59 -0500 | [diff] [blame] | 516 | void VISIBLE16 |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 517 | handle_08(void) |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 518 | { |
Kevin O'Connor | 15c1f22 | 2008-06-12 22:59:43 -0400 | [diff] [blame] | 519 | debug_isr(DEBUG_ISR_08); |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 520 | |
| 521 | floppy_tick(); |
| 522 | |
| 523 | u32 counter = GET_BDA(timer_counter); |
| 524 | counter++; |
| 525 | // compare to one days worth of timer ticks at 18.2 hz |
Kevin O'Connor | 6aee52d | 2009-09-27 20:07:40 -0400 | [diff] [blame] | 526 | if (counter >= TICKS_PER_DAY) { |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 527 | // there has been a midnight rollover at this point |
| 528 | counter = 0; |
| 529 | SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1); |
| 530 | } |
| 531 | |
| 532 | SET_BDA(timer_counter, counter); |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 533 | |
Kevin O'Connor | 0e88576 | 2010-05-01 22:14:40 -0400 | [diff] [blame] | 534 | usb_check_event(); |
Kevin O'Connor | 114592f | 2009-09-28 21:32:08 -0400 | [diff] [blame] | 535 | |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 536 | // chain to user timer tick INT #0x1c |
Kevin O'Connor | a83ff55 | 2009-01-01 21:00:59 -0500 | [diff] [blame] | 537 | u32 eax=0, flags; |
| 538 | call16_simpint(0x1c, &eax, &flags); |
Kevin O'Connor | ed12849 | 2008-03-11 11:14:59 -0400 | [diff] [blame] | 539 | |
Kevin O'Connor | f54c150 | 2008-06-14 15:56:16 -0400 | [diff] [blame] | 540 | eoi_pic1(); |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 541 | } |
| 542 | |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 543 | |
| 544 | /**************************************************************** |
| 545 | * Periodic timer |
| 546 | ****************************************************************/ |
| 547 | |
Kevin O'Connor | ad90159 | 2009-12-13 11:25:25 -0500 | [diff] [blame] | 548 | void |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 549 | useRTC(void) |
Kevin O'Connor | ad90159 | 2009-12-13 11:25:25 -0500 | [diff] [blame] | 550 | { |
| 551 | u16 ebda_seg = get_ebda_seg(); |
| 552 | int count = GET_EBDA2(ebda_seg, RTCusers); |
| 553 | SET_EBDA2(ebda_seg, RTCusers, count+1); |
| 554 | if (count) |
| 555 | return; |
| 556 | // Turn on the Periodic Interrupt timer |
| 557 | u8 bRegister = inb_cmos(CMOS_STATUS_B); |
| 558 | outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B); |
| 559 | } |
| 560 | |
| 561 | void |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 562 | releaseRTC(void) |
Kevin O'Connor | ad90159 | 2009-12-13 11:25:25 -0500 | [diff] [blame] | 563 | { |
| 564 | u16 ebda_seg = get_ebda_seg(); |
| 565 | int count = GET_EBDA2(ebda_seg, RTCusers); |
| 566 | SET_EBDA2(ebda_seg, RTCusers, count-1); |
| 567 | if (count != 1) |
| 568 | return; |
| 569 | // Clear the Periodic Interrupt. |
| 570 | u8 bRegister = inb_cmos(CMOS_STATUS_B); |
| 571 | outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B); |
| 572 | } |
| 573 | |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 574 | static int |
Kevin O'Connor | 72743f1 | 2008-05-24 23:04:09 -0400 | [diff] [blame] | 575 | set_usertimer(u32 usecs, u16 seg, u16 offset) |
Kevin O'Connor | bdce35f | 2008-02-26 21:33:14 -0500 | [diff] [blame] | 576 | { |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 577 | if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING) |
| 578 | return -1; |
| 579 | |
Kevin O'Connor | bdce35f | 2008-02-26 21:33:14 -0500 | [diff] [blame] | 580 | // Interval not already set. |
| 581 | SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte. |
Kevin O'Connor | 9f98542 | 2009-09-09 11:34:39 -0400 | [diff] [blame] | 582 | SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset)); |
Kevin O'Connor | 72743f1 | 2008-05-24 23:04:09 -0400 | [diff] [blame] | 583 | SET_BDA(user_wait_timeout, usecs); |
Kevin O'Connor | ad90159 | 2009-12-13 11:25:25 -0500 | [diff] [blame] | 584 | useRTC(); |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 585 | return 0; |
| 586 | } |
| 587 | |
| 588 | static void |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 589 | clear_usertimer(void) |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 590 | { |
Kevin O'Connor | ad90159 | 2009-12-13 11:25:25 -0500 | [diff] [blame] | 591 | if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)) |
| 592 | return; |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 593 | // Turn off status byte. |
| 594 | SET_BDA(rtc_wait_flag, 0); |
Kevin O'Connor | ad90159 | 2009-12-13 11:25:25 -0500 | [diff] [blame] | 595 | releaseRTC(); |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 596 | } |
| 597 | |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 598 | #define RET_ECLOCKINUSE 0x83 |
| 599 | |
Kevin O'Connor | d21c089 | 2008-11-26 17:02:43 -0500 | [diff] [blame] | 600 | // Wait for CX:DX microseconds |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 601 | void |
| 602 | handle_1586(struct bregs *regs) |
| 603 | { |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 604 | // Use the rtc to wait for the specified time. |
| 605 | u8 statusflag = 0; |
| 606 | u32 count = (regs->cx << 16) | regs->dx; |
| 607 | int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag); |
| 608 | if (ret) { |
Kevin O'Connor | dfefeb5 | 2009-12-13 13:04:17 -0500 | [diff] [blame] | 609 | set_code_invalid(regs, RET_ECLOCKINUSE); |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 610 | return; |
| 611 | } |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 612 | while (!statusflag) |
Kevin O'Connor | ee2efa7 | 2009-09-20 15:33:08 -0400 | [diff] [blame] | 613 | wait_irq(); |
Kevin O'Connor | bc2aecd | 2008-11-28 16:40:06 -0500 | [diff] [blame] | 614 | set_success(regs); |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 615 | } |
| 616 | |
| 617 | // Set Interval requested. |
| 618 | static void |
| 619 | handle_158300(struct bregs *regs) |
| 620 | { |
| 621 | int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx); |
| 622 | if (ret) |
| 623 | // Interval already set. |
Kevin O'Connor | dfefeb5 | 2009-12-13 13:04:17 -0500 | [diff] [blame] | 624 | set_code_invalid(regs, RET_EUNSUPPORTED); |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 625 | else |
| 626 | set_success(regs); |
Kevin O'Connor | bdce35f | 2008-02-26 21:33:14 -0500 | [diff] [blame] | 627 | } |
| 628 | |
| 629 | // Clear interval requested |
| 630 | static void |
| 631 | handle_158301(struct bregs *regs) |
| 632 | { |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 633 | clear_usertimer(); |
| 634 | set_success(regs); |
Kevin O'Connor | bdce35f | 2008-02-26 21:33:14 -0500 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | static void |
| 638 | handle_1583XX(struct bregs *regs) |
| 639 | { |
Kevin O'Connor | dfefeb5 | 2009-12-13 13:04:17 -0500 | [diff] [blame] | 640 | set_code_unimplemented(regs, RET_EUNSUPPORTED); |
Kevin O'Connor | bdce35f | 2008-02-26 21:33:14 -0500 | [diff] [blame] | 641 | regs->al--; |
Kevin O'Connor | bdce35f | 2008-02-26 21:33:14 -0500 | [diff] [blame] | 642 | } |
| 643 | |
| 644 | void |
| 645 | handle_1583(struct bregs *regs) |
| 646 | { |
| 647 | switch (regs->al) { |
| 648 | case 0x00: handle_158300(regs); break; |
| 649 | case 0x01: handle_158301(regs); break; |
| 650 | default: handle_1583XX(regs); break; |
| 651 | } |
| 652 | } |
| 653 | |
Kevin O'Connor | 6aee52d | 2009-09-27 20:07:40 -0400 | [diff] [blame] | 654 | #define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024) |
| 655 | |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 656 | // int70h: IRQ8 - CMOS RTC |
Kevin O'Connor | 1978676 | 2008-03-05 21:09:59 -0500 | [diff] [blame] | 657 | void VISIBLE16 |
Kevin O'Connor | 1ca05b0 | 2010-01-03 17:43:37 -0500 | [diff] [blame] | 658 | handle_70(void) |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 659 | { |
Kevin O'Connor | 15c1f22 | 2008-06-12 22:59:43 -0400 | [diff] [blame] | 660 | debug_isr(DEBUG_ISR_70); |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 661 | |
| 662 | // Check which modes are enabled and have occurred. |
| 663 | u8 registerB = inb_cmos(CMOS_STATUS_B); |
| 664 | u8 registerC = inb_cmos(CMOS_STATUS_C); |
| 665 | |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 666 | if (!(registerB & (RTC_B_PIE|RTC_B_AIE))) |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 667 | goto done; |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 668 | if (registerC & RTC_B_AIE) { |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 669 | // Handle Alarm Interrupt. |
Kevin O'Connor | a83ff55 | 2009-01-01 21:00:59 -0500 | [diff] [blame] | 670 | u32 eax=0, flags; |
| 671 | call16_simpint(0x4a, &eax, &flags); |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 672 | } |
Kevin O'Connor | f358759 | 2009-02-15 13:02:56 -0500 | [diff] [blame] | 673 | if (!(registerC & RTC_B_PIE)) |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 674 | goto done; |
| 675 | |
| 676 | // Handle Periodic Interrupt. |
| 677 | |
Kevin O'Connor | ad90159 | 2009-12-13 11:25:25 -0500 | [diff] [blame] | 678 | check_preempt(); |
| 679 | |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 680 | if (!GET_BDA(rtc_wait_flag)) |
| 681 | goto done; |
| 682 | |
| 683 | // Wait Interval (Int 15, AH=83) active. |
| 684 | u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds. |
Kevin O'Connor | 6aee52d | 2009-09-27 20:07:40 -0400 | [diff] [blame] | 685 | if (time < USEC_PER_RTC) { |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 686 | // Done waiting - write to specified flag byte. |
Kevin O'Connor | 9f98542 | 2009-09-09 11:34:39 -0400 | [diff] [blame] | 687 | struct segoff_s segoff = GET_BDA(user_wait_complete_flag); |
| 688 | u16 ptr_seg = segoff.seg; |
| 689 | u8 *ptr_far = (u8*)(segoff.offset+0); |
| 690 | u8 oldval = GET_FARVAR(ptr_seg, *ptr_far); |
| 691 | SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80); |
Kevin O'Connor | 5be0490 | 2008-05-18 17:12:06 -0400 | [diff] [blame] | 692 | |
| 693 | clear_usertimer(); |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 694 | } else { |
| 695 | // Continue waiting. |
Kevin O'Connor | 6aee52d | 2009-09-27 20:07:40 -0400 | [diff] [blame] | 696 | time -= USEC_PER_RTC; |
Kevin O'Connor | 38fcbfe | 2008-02-25 22:30:47 -0500 | [diff] [blame] | 697 | SET_BDA(user_wait_timeout, time); |
| 698 | } |
| 699 | |
| 700 | done: |
Kevin O'Connor | f54c150 | 2008-06-14 15:56:16 -0400 | [diff] [blame] | 701 | eoi_pic2(); |
Kevin O'Connor | f076a3e | 2008-02-25 22:25:15 -0500 | [diff] [blame] | 702 | } |