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Kevin O'Connorf076a3e2008-02-25 22:25:15 -05001// 16bit code to handle system clocks.
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2002 MandrakeSoft S.A.
5//
6// This file may be distributed under the terms of the GNU GPLv3 license.
7
Kevin O'Connor9521e262008-07-04 13:04:29 -04008#include "biosvar.h" // SET_BDA
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05009#include "util.h" // debug_enter
10#include "disk.h" // floppy_tick
Kevin O'Connor4b60c002008-02-25 22:29:55 -050011#include "cmos.h" // inb_cmos
Kevin O'Connorf54c1502008-06-14 15:56:16 -040012#include "pic.h" // unmask_pic1
Kevin O'Connor9521e262008-07-04 13:04:29 -040013#include "bregs.h" // struct bregs
Kevin O'Connor4b60c002008-02-25 22:29:55 -050014
Kevin O'Connor5be04902008-05-18 17:12:06 -040015// RTC register flags
16#define RTC_A_UIP 0x80
17#define RTC_B_SET 0x80
18#define RTC_B_PIE 0x40
19#define RTC_B_AIE 0x20
20#define RTC_B_UIE 0x10
21
22
23/****************************************************************
24 * Init
25 ****************************************************************/
26
Kevin O'Connor4b60c002008-02-25 22:29:55 -050027static void
Kevin O'Connore6eb3f52008-04-13 17:37:41 -040028pit_setup()
29{
30 // timer0: binary count, 16bit count, mode 2
31 outb(0x34, PORT_PIT_MODE);
32 // maximum count of 0000H = 18.2Hz
33 outb(0x0, PORT_PIT_COUNTER0);
34 outb(0x0, PORT_PIT_COUNTER0);
35}
36
37static u32
38bcd2bin(u8 val)
39{
40 return (val & 0xf) + ((val >> 4) * 10);
41}
42
43void
44timer_setup()
45{
Kevin O'Connor35192dd2008-06-08 19:18:33 -040046 dprintf(3, "init timer\n");
Kevin O'Connore6eb3f52008-04-13 17:37:41 -040047 pit_setup();
48
49 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
50 u32 ticks = (seconds * 18206507) / 1000000;
51 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
52 ticks += (minutes * 10923904) / 10000;
53 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
54 ticks += (hours * 65543427) / 1000;
55 SET_BDA(timer_counter, ticks);
56 SET_BDA(timer_rollover, 0);
Kevin O'Connorf54c1502008-06-14 15:56:16 -040057
58 // Enable IRQ0 (handle_08)
59 unmask_pic1(PIC1_IRQ0);
Kevin O'Connore6eb3f52008-04-13 17:37:41 -040060}
61
62static void
Kevin O'Connor4b60c002008-02-25 22:29:55 -050063init_rtc()
64{
65 outb_cmos(0x26, CMOS_STATUS_A);
66 outb_cmos(0x02, CMOS_STATUS_B);
67 inb_cmos(CMOS_STATUS_C);
68 inb_cmos(CMOS_STATUS_D);
69}
70
Kevin O'Connor5be04902008-05-18 17:12:06 -040071
72/****************************************************************
73 * Standard clock functions
74 ****************************************************************/
75
Kevin O'Connor4b60c002008-02-25 22:29:55 -050076static u8
77rtc_updating()
78{
79 // This function checks to see if the update-in-progress bit
80 // is set in CMOS Status Register A. If not, it returns 0.
81 // If it is set, it tries to wait until there is a transition
82 // to 0, and will return 0 if such a transition occurs. A 1
83 // is returned only after timing out. The maximum period
84 // that this bit should be set is constrained to 244useconds.
85 // The count I use below guarantees coverage or more than
86 // this time, with any reasonable IPS setting.
87
88 u16 count = 25000;
89 while (--count != 0) {
90 if ( (inb_cmos(CMOS_STATUS_A) & 0x80) == 0 )
91 return 0;
92 }
93 return 1; // update-in-progress never transitioned to 0
94}
95
96// get current clock count
97static void
98handle_1a00(struct bregs *regs)
99{
100 u32 ticks = GET_BDA(timer_counter);
101 regs->cx = ticks >> 16;
102 regs->dx = ticks;
103 regs->al = GET_BDA(timer_rollover);
104 SET_BDA(timer_rollover, 0); // reset flag
Kevin O'Connor6c781222008-03-09 12:19:23 -0400105 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500106}
107
108// Set Current Clock Count
109static void
110handle_1a01(struct bregs *regs)
111{
112 u32 ticks = (regs->cx << 16) | regs->dx;
113 SET_BDA(timer_counter, ticks);
114 SET_BDA(timer_rollover, 0); // reset flag
115 regs->ah = 0;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400116 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500117}
118
119// Read CMOS Time
120static void
121handle_1a02(struct bregs *regs)
122{
123 if (rtc_updating()) {
Kevin O'Connor6c781222008-03-09 12:19:23 -0400124 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500125 return;
126 }
127
128 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
129 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
130 regs->ch = inb_cmos(CMOS_RTC_HOURS);
131 regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
132 regs->ah = 0;
133 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400134 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500135}
136
137// Set CMOS Time
138static void
139handle_1a03(struct bregs *regs)
140{
141 // Using a debugger, I notice the following masking/setting
142 // of bits in Status Register B, by setting Reg B to
143 // a few values and getting its value after INT 1A was called.
144 //
145 // try#1 try#2 try#3
146 // before 1111 1101 0111 1101 0000 0000
147 // after 0110 0010 0110 0010 0000 0010
148 //
149 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
150 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
151 if (rtc_updating()) {
152 init_rtc();
153 // fall through as if an update were not in progress
154 }
155 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
156 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
157 outb_cmos(regs->ch, CMOS_RTC_HOURS);
158 // Set Daylight Savings time enabled bit to requested value
159 u8 val8 = (inb_cmos(CMOS_STATUS_B) & 0x60) | 0x02 | (regs->dl & 0x01);
160 outb_cmos(val8, CMOS_STATUS_B);
161 regs->ah = 0;
162 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400163 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500164}
165
166// Read CMOS Date
167static void
168handle_1a04(struct bregs *regs)
169{
170 regs->ah = 0;
171 if (rtc_updating()) {
Kevin O'Connor6c781222008-03-09 12:19:23 -0400172 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500173 return;
174 }
175 regs->cl = inb_cmos(CMOS_RTC_YEAR);
176 regs->dh = inb_cmos(CMOS_RTC_MONTH);
177 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
178 regs->ch = inb_cmos(CMOS_CENTURY);
179 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400180 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500181}
182
183// Set CMOS Date
184static void
185handle_1a05(struct bregs *regs)
186{
187 // Using a debugger, I notice the following masking/setting
188 // of bits in Status Register B, by setting Reg B to
189 // a few values and getting its value after INT 1A was called.
190 //
191 // try#1 try#2 try#3 try#4
192 // before 1111 1101 0111 1101 0000 0010 0000 0000
193 // after 0110 1101 0111 1101 0000 0010 0000 0000
194 //
195 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
196 // My assumption: RegB = (RegB & 01111111b)
197 if (rtc_updating()) {
198 init_rtc();
Kevin O'Connor6c781222008-03-09 12:19:23 -0400199 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500200 return;
201 }
202 outb_cmos(regs->cl, CMOS_RTC_YEAR);
203 outb_cmos(regs->dh, CMOS_RTC_MONTH);
204 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
205 outb_cmos(regs->ch, CMOS_CENTURY);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400206 // clear halt-clock bit
207 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500208 outb_cmos(val8, CMOS_STATUS_B);
209 regs->ah = 0;
210 regs->al = val8; // AL = val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400211 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500212}
213
214// Set Alarm Time in CMOS
215static void
216handle_1a06(struct bregs *regs)
217{
218 // Using a debugger, I notice the following masking/setting
219 // of bits in Status Register B, by setting Reg B to
220 // a few values and getting its value after INT 1A was called.
221 //
222 // try#1 try#2 try#3
223 // before 1101 1111 0101 1111 0000 0000
224 // after 0110 1111 0111 1111 0010 0000
225 //
226 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
227 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
228 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
229 regs->ax = 0;
230 if (val8 & 0x20) {
231 // Alarm interrupt enabled already
Kevin O'Connor6c781222008-03-09 12:19:23 -0400232 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500233 return;
234 }
235 if (rtc_updating()) {
236 init_rtc();
237 // fall through as if an update were not in progress
238 }
239 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
240 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
241 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400242 unmask_pic2(PIC2_IRQ8); // enable IRQ 8
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500243 // enable Status Reg B alarm bit, clear halt clock bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400244 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
Kevin O'Connor6c781222008-03-09 12:19:23 -0400245 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500246}
247
248// Turn off Alarm
249static void
250handle_1a07(struct bregs *regs)
251{
252 // Using a debugger, I notice the following masking/setting
253 // of bits in Status Register B, by setting Reg B to
254 // a few values and getting its value after INT 1A was called.
255 //
256 // try#1 try#2 try#3 try#4
257 // before 1111 1101 0111 1101 0010 0000 0010 0010
258 // after 0100 0101 0101 0101 0000 0000 0000 0010
259 //
260 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
261 // My assumption: RegB = (RegB & 01010111b)
262 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
263 // clear clock-halt bit, disable alarm bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400264 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500265 regs->ah = 0;
266 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400267 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500268}
269
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500270// Unsupported
271static void
272handle_1aXX(struct bregs *regs)
273{
Kevin O'Connor6c781222008-03-09 12:19:23 -0400274 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500275}
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500276
277// INT 1Ah Time-of-day Service Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500278void VISIBLE16
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500279handle_1a(struct bregs *regs)
280{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400281 debug_enter(regs, DEBUG_HDL_1a);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500282 switch (regs->ah) {
283 case 0x00: handle_1a00(regs); break;
284 case 0x01: handle_1a01(regs); break;
285 case 0x02: handle_1a02(regs); break;
286 case 0x03: handle_1a03(regs); break;
287 case 0x04: handle_1a04(regs); break;
288 case 0x05: handle_1a05(regs); break;
289 case 0x06: handle_1a06(regs); break;
290 case 0x07: handle_1a07(regs); break;
291 case 0xb1: handle_1ab1(regs); break;
292 default: handle_1aXX(regs); break;
293 }
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500294}
295
296// User Timer Tick
Kevin O'Connor19786762008-03-05 21:09:59 -0500297void VISIBLE16
Kevin O'Connored128492008-03-11 11:14:59 -0400298handle_1c()
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500299{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400300 debug_isr(DEBUG_ISR_1c);
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500301}
302
303// INT 08h System Timer ISR Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500304void VISIBLE16
Kevin O'Connored128492008-03-11 11:14:59 -0400305handle_08()
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500306{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400307 debug_isr(DEBUG_ISR_08);
Kevin O'Connored128492008-03-11 11:14:59 -0400308 irq_enable();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500309
310 floppy_tick();
311
312 u32 counter = GET_BDA(timer_counter);
313 counter++;
314 // compare to one days worth of timer ticks at 18.2 hz
315 if (counter >= 0x001800B0) {
316 // there has been a midnight rollover at this point
317 counter = 0;
318 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
319 }
320
321 SET_BDA(timer_counter, counter);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500322
323 // chain to user timer tick INT #0x1c
324 struct bregs br;
325 memset(&br, 0, sizeof(br));
326 call16_int(0x1c, &br);
327
Kevin O'Connored128492008-03-11 11:14:59 -0400328 irq_disable();
329
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400330 eoi_pic1();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500331}
332
Kevin O'Connor5be04902008-05-18 17:12:06 -0400333
334/****************************************************************
335 * Periodic timer
336 ****************************************************************/
337
338static int
Kevin O'Connor72743f12008-05-24 23:04:09 -0400339set_usertimer(u32 usecs, u16 seg, u16 offset)
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500340{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400341 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
342 return -1;
343
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500344 // Interval not already set.
345 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
Kevin O'Connor5be04902008-05-18 17:12:06 -0400346 SET_BDA(ptr_user_wait_complete_flag, (seg << 16) | offset);
Kevin O'Connor72743f12008-05-24 23:04:09 -0400347 SET_BDA(user_wait_timeout, usecs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500348
349 // Unmask IRQ8 so INT70 will get through.
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400350 unmask_pic2(PIC2_IRQ8);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500351 // Turn on the Periodic Interrupt timer
352 u8 bRegister = inb_cmos(CMOS_STATUS_B);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400353 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500354
Kevin O'Connor5be04902008-05-18 17:12:06 -0400355 return 0;
356}
357
358static void
359clear_usertimer()
360{
361 // Turn off status byte.
362 SET_BDA(rtc_wait_flag, 0);
363 // Clear the Periodic Interrupt.
364 u8 bRegister = inb_cmos(CMOS_STATUS_B);
365 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
366}
367
368// Sleep for n microseconds.
369int
370usleep(u32 count)
371{
372#ifdef MODE16
373 // In 16bit mode, use the rtc to wait for the specified time.
374 u8 statusflag = 0;
375 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
376 if (ret)
377 return -1;
378 irq_enable();
379 while (!statusflag)
380 cpu_relax();
381 irq_disable();
382 return 0;
383#else
384 // In 32bit mode, we need to call into 16bit mode to sleep.
385 struct bregs br;
386 memset(&br, 0, sizeof(br));
387 br.ah = 0x86;
388 br.cx = count >> 16;
389 br.dx = count;
390 call16_int(0x15, &br);
391 if (br.flags & F_CF)
392 return -1;
393 return 0;
394#endif
395}
396
397#define RET_ECLOCKINUSE 0x83
398
399// Wait for CX:DX microseconds. currently using the
400// refresh request port 0x61 bit4, toggling every 15usec
401void
402handle_1586(struct bregs *regs)
403{
404 int ret = usleep((regs->cx << 16) | regs->dx);
405 if (ret)
406 set_code_fail(regs, RET_ECLOCKINUSE);
407 else
408 set_success(regs);
409}
410
411// Set Interval requested.
412static void
413handle_158300(struct bregs *regs)
414{
415 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
416 if (ret)
417 // Interval already set.
418 set_code_fail(regs, RET_EUNSUPPORTED);
419 else
420 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500421}
422
423// Clear interval requested
424static void
425handle_158301(struct bregs *regs)
426{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400427 clear_usertimer();
428 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500429}
430
431static void
432handle_1583XX(struct bregs *regs)
433{
Kevin O'Connor6c781222008-03-09 12:19:23 -0400434 set_code_fail(regs, RET_EUNSUPPORTED);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500435 regs->al--;
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500436}
437
438void
439handle_1583(struct bregs *regs)
440{
441 switch (regs->al) {
442 case 0x00: handle_158300(regs); break;
443 case 0x01: handle_158301(regs); break;
444 default: handle_1583XX(regs); break;
445 }
446}
447
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500448// int70h: IRQ8 - CMOS RTC
Kevin O'Connor19786762008-03-05 21:09:59 -0500449void VISIBLE16
Kevin O'Connored128492008-03-11 11:14:59 -0400450handle_70()
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500451{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400452 debug_isr(DEBUG_ISR_70);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500453
454 // Check which modes are enabled and have occurred.
455 u8 registerB = inb_cmos(CMOS_STATUS_B);
456 u8 registerC = inb_cmos(CMOS_STATUS_C);
457
Kevin O'Connor5be04902008-05-18 17:12:06 -0400458 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500459 goto done;
460 if (registerC & 0x20) {
461 // Handle Alarm Interrupt.
462 struct bregs br;
463 memset(&br, 0, sizeof(br));
464 call16_int(0x4a, &br);
Kevin O'Connor7a558e42008-03-11 20:38:33 -0400465 irq_disable();
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500466 }
467 if (!(registerC & 0x40))
468 goto done;
469
470 // Handle Periodic Interrupt.
471
472 if (!GET_BDA(rtc_wait_flag))
473 goto done;
474
475 // Wait Interval (Int 15, AH=83) active.
476 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
477 if (time < 0x3D1) {
Kevin O'Connor5be04902008-05-18 17:12:06 -0400478 // Done waiting - write to specified flag byte.
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500479 u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
480 u16 segment = segoff >> 16;
481 u16 offset = segoff & 0xffff;
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500482 u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
483 SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400484
485 clear_usertimer();
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500486 } else {
487 // Continue waiting.
488 time -= 0x3D1;
489 SET_BDA(user_wait_timeout, time);
490 }
491
492done:
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400493 eoi_pic2();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500494}