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Kevin O'Connorf076a3e2008-02-25 22:25:15 -05001// 16bit code to handle system clocks.
2//
Kevin O'Connorabf31d32010-07-26 22:33:54 -04003// Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05004// Copyright (C) 2002 MandrakeSoft S.A.
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05007
Kevin O'Connor9521e262008-07-04 13:04:29 -04008#include "biosvar.h" // SET_BDA
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05009#include "util.h" // debug_enter
10#include "disk.h" // floppy_tick
Kevin O'Connor4b60c002008-02-25 22:29:55 -050011#include "cmos.h" // inb_cmos
Kevin O'Connord21c0892008-11-26 17:02:43 -050012#include "pic.h" // eoi_pic1
Kevin O'Connor9521e262008-07-04 13:04:29 -040013#include "bregs.h" // struct bregs
Kevin O'Connor15157a32008-12-13 11:10:37 -050014#include "biosvar.h" // GET_GLOBAL
Kevin O'Connor0e885762010-05-01 22:14:40 -040015#include "usb-hid.h" // usb_check_event
Kevin O'Connor4b60c002008-02-25 22:29:55 -050016
Kevin O'Connor5be04902008-05-18 17:12:06 -040017// RTC register flags
18#define RTC_A_UIP 0x80
Kevin O'Connorf3587592009-02-15 13:02:56 -050019
20#define RTC_B_SET 0x80
21#define RTC_B_PIE 0x40
22#define RTC_B_AIE 0x20
23#define RTC_B_UIE 0x10
24#define RTC_B_BIN 0x04
25#define RTC_B_24HR 0x02
26#define RTC_B_DSE 0x01
27
Kevin O'Connor5be04902008-05-18 17:12:06 -040028
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050029// Bits for PORT_PS2_CTRLB
30#define PPCB_T2GATE (1<<0)
31#define PPCB_SPKR (1<<1)
32#define PPCB_T2OUT (1<<5)
33
34// Bits for PORT_PIT_MODE
35#define PM_SEL_TIMER0 (0<<6)
36#define PM_SEL_TIMER1 (1<<6)
37#define PM_SEL_TIMER2 (2<<6)
38#define PM_SEL_READBACK (3<<6)
39#define PM_ACCESS_LATCH (0<<4)
40#define PM_ACCESS_LOBYTE (1<<4)
41#define PM_ACCESS_HIBYTE (2<<4)
42#define PM_ACCESS_WORD (3<<4)
43#define PM_MODE0 (0<<1)
44#define PM_MODE1 (1<<1)
45#define PM_MODE2 (2<<1)
46#define PM_MODE3 (3<<1)
47#define PM_MODE4 (4<<1)
48#define PM_MODE5 (5<<1)
49#define PM_CNT_BINARY (0<<0)
50#define PM_CNT_BCD (1<<0)
51
52
53/****************************************************************
54 * TSC timer
55 ****************************************************************/
56
Kevin O'Connor6aee52d2009-09-27 20:07:40 -040057#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050058
Kevin O'Connor372e0712009-09-09 09:51:31 -040059u32 cpu_khz VAR16VISIBLE;
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050060
61static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -050062calibrate_tsc(void)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050063{
64 // Setup "timer2"
65 u8 orig = inb(PORT_PS2_CTRLB);
66 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
67 /* binary, mode 0, LSB/MSB, Ch 2 */
68 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
69 /* LSB of ticks */
70 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
71 /* MSB of ticks */
72 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
73
74 u64 start = rdtscll();
75 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
76 ;
77 u64 end = rdtscll();
78
79 // Restore PORT_PS2_CTRLB
80 outb(orig, PORT_PS2_CTRLB);
81
82 // Store calibrated cpu khz.
83 u64 diff = end - start;
84 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
85 , (u32)start, (u32)end, (u32)diff);
86 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
Kevin O'Connor15157a32008-12-13 11:10:37 -050087 SET_GLOBAL(cpu_khz, hz / 1000);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050088
89 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
90}
91
92static void
Kevin O'Connor89eb6242009-10-22 22:30:37 -040093tscdelay(u64 diff)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050094{
95 u64 start = rdtscll();
96 u64 end = start + diff;
Kevin O'Connor144817b2010-05-23 10:46:49 -040097 while (!check_tsc(end))
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050098 cpu_relax();
99}
100
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400101static void
102tscsleep(u64 diff)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500103{
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400104 u64 start = rdtscll();
105 u64 end = start + diff;
Kevin O'Connor144817b2010-05-23 10:46:49 -0400106 while (!check_tsc(end))
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400107 yield();
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500108}
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400109
110void ndelay(u32 count) {
111 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500112}
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400113void udelay(u32 count) {
114 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000);
115}
116void mdelay(u32 count) {
117 tscdelay(count * GET_GLOBAL(cpu_khz));
118}
119
120void nsleep(u32 count) {
121 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000);
122}
123void usleep(u32 count) {
124 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000);
125}
126void msleep(u32 count) {
127 tscsleep(count * GET_GLOBAL(cpu_khz));
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500128}
129
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500130// Return the TSC value that is 'msecs' time in the future.
131u64
132calc_future_tsc(u32 msecs)
133{
Kevin O'Connor15157a32008-12-13 11:10:37 -0500134 u32 khz = GET_GLOBAL(cpu_khz);
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500135 return rdtscll() + ((u64)khz * msecs);
136}
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400137u64
138calc_future_tsc_usec(u32 usecs)
139{
140 u32 khz = GET_GLOBAL(cpu_khz);
141 return rdtscll() + ((u64)(khz/1000) * usecs);
142}
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500143
Kevin O'Connor5be04902008-05-18 17:12:06 -0400144
145/****************************************************************
146 * Init
147 ****************************************************************/
148
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500149static int
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500150rtc_updating(void)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500151{
152 // This function checks to see if the update-in-progress bit
153 // is set in CMOS Status Register A. If not, it returns 0.
154 // If it is set, it tries to wait until there is a transition
155 // to 0, and will return 0 if such a transition occurs. A -1
156 // is returned only after timing out. The maximum period
Kevin O'Connor4f5586c2009-02-16 10:14:10 -0500157 // that this bit should be set is constrained to (1984+244)
Kevin O'Connor11cc6622010-03-13 23:04:41 -0500158 // useconds, but we wait for longer just to be sure.
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500159
Kevin O'Connorf3587592009-02-15 13:02:56 -0500160 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500161 return 0;
Kevin O'Connor11cc6622010-03-13 23:04:41 -0500162 u64 end = calc_future_tsc(15);
163 for (;;) {
Kevin O'Connorf3587592009-02-15 13:02:56 -0500164 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500165 return 0;
Kevin O'Connor144817b2010-05-23 10:46:49 -0400166 if (check_tsc(end))
Kevin O'Connor11cc6622010-03-13 23:04:41 -0500167 // update-in-progress never transitioned to 0
168 return -1;
169 yield();
170 }
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500171}
172
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500173static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500174pit_setup(void)
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400175{
176 // timer0: binary count, 16bit count, mode 2
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500177 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400178 // maximum count of 0000H = 18.2Hz
179 outb(0x0, PORT_PIT_COUNTER0);
180 outb(0x0, PORT_PIT_COUNTER0);
181}
182
Kevin O'Connorf3587592009-02-15 13:02:56 -0500183static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500184init_rtc(void)
Kevin O'Connorf3587592009-02-15 13:02:56 -0500185{
Kevin O'Connor4f5586c2009-02-16 10:14:10 -0500186 outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
Kevin O'Connorf3587592009-02-15 13:02:56 -0500187 u8 regB = inb_cmos(CMOS_STATUS_B);
188 outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
189 inb_cmos(CMOS_STATUS_C);
190 inb_cmos(CMOS_STATUS_D);
191}
192
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400193static u32
194bcd2bin(u8 val)
195{
196 return (val & 0xf) + ((val >> 4) * 10);
197}
198
199void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500200timer_setup(void)
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400201{
Kevin O'Connor35192dd2008-06-08 19:18:33 -0400202 dprintf(3, "init timer\n");
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500203 calibrate_tsc();
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400204 pit_setup();
205
Kevin O'Connorf3587592009-02-15 13:02:56 -0500206 init_rtc();
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500207 rtc_updating();
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400208 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400209 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400210 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400211 u32 ticks = (hours * 60 + minutes) * 60 + seconds;
212 ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400213 SET_BDA(timer_counter, ticks);
214 SET_BDA(timer_rollover, 0);
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400215
Kevin O'Connord21c0892008-11-26 17:02:43 -0500216 enable_hwirq(0, entry_08);
217 enable_hwirq(8, entry_70);
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400218}
219
Kevin O'Connor5be04902008-05-18 17:12:06 -0400220
221/****************************************************************
222 * Standard clock functions
223 ****************************************************************/
224
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400225#define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
226
227// Calculate the timer value at 'count' number of full timer ticks in
228// the future.
229u32
230calc_future_timer_ticks(u32 count)
231{
232 return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY;
233}
Kevin O'Connorbb685912010-05-23 12:40:40 -0400234
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400235// Return the timer value that is 'msecs' time in the future.
236u32
237calc_future_timer(u32 msecs)
238{
Kevin O'Connorbb685912010-05-23 12:40:40 -0400239 if (!msecs)
240 return GET_BDA(timer_counter);
Kevin O'Connorabf31d32010-07-26 22:33:54 -0400241 u32 kticks = DIV_ROUND_UP((u64)msecs * PIT_TICK_RATE, PIT_TICK_INTERVAL);
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400242 u32 ticks = DIV_ROUND_UP(kticks, 1000);
243 return calc_future_timer_ticks(ticks);
244}
Kevin O'Connorbb685912010-05-23 12:40:40 -0400245
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400246// Check if the given timer value has passed.
247int
248check_timer(u32 end)
249{
250 return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY)
251 < (TICKS_PER_DAY/2));
252}
253
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500254// get current clock count
255static void
256handle_1a00(struct bregs *regs)
257{
Kevin O'Connor68c51392010-03-13 22:23:44 -0500258 yield();
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500259 u32 ticks = GET_BDA(timer_counter);
260 regs->cx = ticks >> 16;
261 regs->dx = ticks;
262 regs->al = GET_BDA(timer_rollover);
263 SET_BDA(timer_rollover, 0); // reset flag
Kevin O'Connor6c781222008-03-09 12:19:23 -0400264 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500265}
266
267// Set Current Clock Count
268static void
269handle_1a01(struct bregs *regs)
270{
271 u32 ticks = (regs->cx << 16) | regs->dx;
272 SET_BDA(timer_counter, ticks);
273 SET_BDA(timer_rollover, 0); // reset flag
Kevin O'Connor15157a32008-12-13 11:10:37 -0500274 // XXX - should use set_code_success()?
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500275 regs->ah = 0;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400276 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500277}
278
279// Read CMOS Time
280static void
281handle_1a02(struct bregs *regs)
282{
283 if (rtc_updating()) {
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500284 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500285 return;
286 }
287
288 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
289 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
290 regs->ch = inb_cmos(CMOS_RTC_HOURS);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500291 regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500292 regs->ah = 0;
293 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400294 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500295}
296
297// Set CMOS Time
298static void
299handle_1a03(struct bregs *regs)
300{
301 // Using a debugger, I notice the following masking/setting
302 // of bits in Status Register B, by setting Reg B to
303 // a few values and getting its value after INT 1A was called.
304 //
305 // try#1 try#2 try#3
306 // before 1111 1101 0111 1101 0000 0000
307 // after 0110 0010 0110 0010 0000 0010
308 //
309 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
310 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
311 if (rtc_updating()) {
312 init_rtc();
313 // fall through as if an update were not in progress
314 }
315 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
316 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
317 outb_cmos(regs->ch, CMOS_RTC_HOURS);
318 // Set Daylight Savings time enabled bit to requested value
Kevin O'Connorf3587592009-02-15 13:02:56 -0500319 u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
320 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500321 outb_cmos(val8, CMOS_STATUS_B);
322 regs->ah = 0;
323 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400324 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500325}
326
327// Read CMOS Date
328static void
329handle_1a04(struct bregs *regs)
330{
331 regs->ah = 0;
332 if (rtc_updating()) {
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500333 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500334 return;
335 }
336 regs->cl = inb_cmos(CMOS_RTC_YEAR);
337 regs->dh = inb_cmos(CMOS_RTC_MONTH);
338 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500339 if (CONFIG_COREBOOT) {
340 if (regs->cl > 0x80)
341 regs->ch = 0x19;
342 else
343 regs->ch = 0x20;
344 } else {
345 regs->ch = inb_cmos(CMOS_CENTURY);
346 }
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500347 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400348 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500349}
350
351// Set CMOS Date
352static void
353handle_1a05(struct bregs *regs)
354{
355 // Using a debugger, I notice the following masking/setting
356 // of bits in Status Register B, by setting Reg B to
357 // a few values and getting its value after INT 1A was called.
358 //
359 // try#1 try#2 try#3 try#4
360 // before 1111 1101 0111 1101 0000 0010 0000 0000
361 // after 0110 1101 0111 1101 0000 0010 0000 0000
362 //
363 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
364 // My assumption: RegB = (RegB & 01111111b)
365 if (rtc_updating()) {
366 init_rtc();
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500367 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500368 return;
369 }
370 outb_cmos(regs->cl, CMOS_RTC_YEAR);
371 outb_cmos(regs->dh, CMOS_RTC_MONTH);
372 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500373 if (!CONFIG_COREBOOT)
374 outb_cmos(regs->ch, CMOS_CENTURY);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400375 // clear halt-clock bit
376 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500377 outb_cmos(val8, CMOS_STATUS_B);
378 regs->ah = 0;
379 regs->al = val8; // AL = val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400380 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500381}
382
383// Set Alarm Time in CMOS
384static void
385handle_1a06(struct bregs *regs)
386{
387 // Using a debugger, I notice the following masking/setting
388 // of bits in Status Register B, by setting Reg B to
389 // a few values and getting its value after INT 1A was called.
390 //
391 // try#1 try#2 try#3
392 // before 1101 1111 0101 1111 0000 0000
393 // after 0110 1111 0111 1111 0010 0000
394 //
395 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
396 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
397 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
398 regs->ax = 0;
Kevin O'Connorf3587592009-02-15 13:02:56 -0500399 if (val8 & RTC_B_AIE) {
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500400 // Alarm interrupt enabled already
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500401 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500402 return;
403 }
404 if (rtc_updating()) {
405 init_rtc();
406 // fall through as if an update were not in progress
407 }
408 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
409 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
410 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500411 // enable Status Reg B alarm bit, clear halt clock bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400412 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
Kevin O'Connor6c781222008-03-09 12:19:23 -0400413 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500414}
415
416// Turn off Alarm
417static void
418handle_1a07(struct bregs *regs)
419{
420 // Using a debugger, I notice the following masking/setting
421 // of bits in Status Register B, by setting Reg B to
422 // a few values and getting its value after INT 1A was called.
423 //
424 // try#1 try#2 try#3 try#4
425 // before 1111 1101 0111 1101 0010 0000 0010 0010
426 // after 0100 0101 0101 0101 0000 0000 0000 0010
427 //
428 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
429 // My assumption: RegB = (RegB & 01010111b)
430 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
431 // clear clock-halt bit, disable alarm bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400432 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500433 regs->ah = 0;
434 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400435 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500436}
437
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500438// Unsupported
439static void
440handle_1aXX(struct bregs *regs)
441{
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500442 set_unimplemented(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500443}
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500444
445// INT 1Ah Time-of-day Service Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500446void VISIBLE16
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500447handle_1a(struct bregs *regs)
448{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400449 debug_enter(regs, DEBUG_HDL_1a);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500450 switch (regs->ah) {
451 case 0x00: handle_1a00(regs); break;
452 case 0x01: handle_1a01(regs); break;
453 case 0x02: handle_1a02(regs); break;
454 case 0x03: handle_1a03(regs); break;
455 case 0x04: handle_1a04(regs); break;
456 case 0x05: handle_1a05(regs); break;
457 case 0x06: handle_1a06(regs); break;
458 case 0x07: handle_1a07(regs); break;
459 case 0xb1: handle_1ab1(regs); break;
460 default: handle_1aXX(regs); break;
461 }
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500462}
463
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500464// INT 08h System Timer ISR Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500465void VISIBLE16
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500466handle_08(void)
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500467{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400468 debug_isr(DEBUG_ISR_08);
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500469
470 floppy_tick();
471
472 u32 counter = GET_BDA(timer_counter);
473 counter++;
474 // compare to one days worth of timer ticks at 18.2 hz
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400475 if (counter >= TICKS_PER_DAY) {
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500476 // there has been a midnight rollover at this point
477 counter = 0;
478 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
479 }
480
481 SET_BDA(timer_counter, counter);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500482
Kevin O'Connor0e885762010-05-01 22:14:40 -0400483 usb_check_event();
Kevin O'Connor114592f2009-09-28 21:32:08 -0400484
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500485 // chain to user timer tick INT #0x1c
Kevin O'Connora83ff552009-01-01 21:00:59 -0500486 u32 eax=0, flags;
487 call16_simpint(0x1c, &eax, &flags);
Kevin O'Connored128492008-03-11 11:14:59 -0400488
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400489 eoi_pic1();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500490}
491
Kevin O'Connor5be04902008-05-18 17:12:06 -0400492
493/****************************************************************
494 * Periodic timer
495 ****************************************************************/
496
Kevin O'Connorad901592009-12-13 11:25:25 -0500497void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500498useRTC(void)
Kevin O'Connorad901592009-12-13 11:25:25 -0500499{
500 u16 ebda_seg = get_ebda_seg();
501 int count = GET_EBDA2(ebda_seg, RTCusers);
502 SET_EBDA2(ebda_seg, RTCusers, count+1);
503 if (count)
504 return;
505 // Turn on the Periodic Interrupt timer
506 u8 bRegister = inb_cmos(CMOS_STATUS_B);
507 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
508}
509
510void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500511releaseRTC(void)
Kevin O'Connorad901592009-12-13 11:25:25 -0500512{
513 u16 ebda_seg = get_ebda_seg();
514 int count = GET_EBDA2(ebda_seg, RTCusers);
515 SET_EBDA2(ebda_seg, RTCusers, count-1);
516 if (count != 1)
517 return;
518 // Clear the Periodic Interrupt.
519 u8 bRegister = inb_cmos(CMOS_STATUS_B);
520 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
521}
522
Kevin O'Connor5be04902008-05-18 17:12:06 -0400523static int
Kevin O'Connor72743f12008-05-24 23:04:09 -0400524set_usertimer(u32 usecs, u16 seg, u16 offset)
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500525{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400526 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
527 return -1;
528
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500529 // Interval not already set.
530 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
Kevin O'Connor9f985422009-09-09 11:34:39 -0400531 SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
Kevin O'Connor72743f12008-05-24 23:04:09 -0400532 SET_BDA(user_wait_timeout, usecs);
Kevin O'Connorad901592009-12-13 11:25:25 -0500533 useRTC();
Kevin O'Connor5be04902008-05-18 17:12:06 -0400534 return 0;
535}
536
537static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500538clear_usertimer(void)
Kevin O'Connor5be04902008-05-18 17:12:06 -0400539{
Kevin O'Connorad901592009-12-13 11:25:25 -0500540 if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING))
541 return;
Kevin O'Connor5be04902008-05-18 17:12:06 -0400542 // Turn off status byte.
543 SET_BDA(rtc_wait_flag, 0);
Kevin O'Connorad901592009-12-13 11:25:25 -0500544 releaseRTC();
Kevin O'Connor5be04902008-05-18 17:12:06 -0400545}
546
Kevin O'Connor5be04902008-05-18 17:12:06 -0400547#define RET_ECLOCKINUSE 0x83
548
Kevin O'Connord21c0892008-11-26 17:02:43 -0500549// Wait for CX:DX microseconds
Kevin O'Connor5be04902008-05-18 17:12:06 -0400550void
551handle_1586(struct bregs *regs)
552{
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500553 // Use the rtc to wait for the specified time.
554 u8 statusflag = 0;
555 u32 count = (regs->cx << 16) | regs->dx;
556 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
557 if (ret) {
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500558 set_code_invalid(regs, RET_ECLOCKINUSE);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500559 return;
560 }
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500561 while (!statusflag)
Kevin O'Connoree2efa72009-09-20 15:33:08 -0400562 wait_irq();
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500563 set_success(regs);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400564}
565
566// Set Interval requested.
567static void
568handle_158300(struct bregs *regs)
569{
570 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
571 if (ret)
572 // Interval already set.
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500573 set_code_invalid(regs, RET_EUNSUPPORTED);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400574 else
575 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500576}
577
578// Clear interval requested
579static void
580handle_158301(struct bregs *regs)
581{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400582 clear_usertimer();
583 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500584}
585
586static void
587handle_1583XX(struct bregs *regs)
588{
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500589 set_code_unimplemented(regs, RET_EUNSUPPORTED);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500590 regs->al--;
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500591}
592
593void
594handle_1583(struct bregs *regs)
595{
596 switch (regs->al) {
597 case 0x00: handle_158300(regs); break;
598 case 0x01: handle_158301(regs); break;
599 default: handle_1583XX(regs); break;
600 }
601}
602
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400603#define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
604
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500605// int70h: IRQ8 - CMOS RTC
Kevin O'Connor19786762008-03-05 21:09:59 -0500606void VISIBLE16
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500607handle_70(void)
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500608{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400609 debug_isr(DEBUG_ISR_70);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500610
611 // Check which modes are enabled and have occurred.
612 u8 registerB = inb_cmos(CMOS_STATUS_B);
613 u8 registerC = inb_cmos(CMOS_STATUS_C);
614
Kevin O'Connor5be04902008-05-18 17:12:06 -0400615 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500616 goto done;
Kevin O'Connorf3587592009-02-15 13:02:56 -0500617 if (registerC & RTC_B_AIE) {
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500618 // Handle Alarm Interrupt.
Kevin O'Connora83ff552009-01-01 21:00:59 -0500619 u32 eax=0, flags;
620 call16_simpint(0x4a, &eax, &flags);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500621 }
Kevin O'Connorf3587592009-02-15 13:02:56 -0500622 if (!(registerC & RTC_B_PIE))
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500623 goto done;
624
625 // Handle Periodic Interrupt.
626
Kevin O'Connorad901592009-12-13 11:25:25 -0500627 check_preempt();
628
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500629 if (!GET_BDA(rtc_wait_flag))
630 goto done;
631
632 // Wait Interval (Int 15, AH=83) active.
633 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400634 if (time < USEC_PER_RTC) {
Kevin O'Connor5be04902008-05-18 17:12:06 -0400635 // Done waiting - write to specified flag byte.
Kevin O'Connor9f985422009-09-09 11:34:39 -0400636 struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
637 u16 ptr_seg = segoff.seg;
638 u8 *ptr_far = (u8*)(segoff.offset+0);
639 u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
640 SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400641
642 clear_usertimer();
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500643 } else {
644 // Continue waiting.
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400645 time -= USEC_PER_RTC;
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500646 SET_BDA(user_wait_timeout, time);
647 }
648
649done:
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400650 eoi_pic2();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500651}