blob: 7735c70a3e994eaeb26405652aecc37c1f64200e [file] [log] [blame]
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05001// 16bit code to handle system clocks.
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2002 MandrakeSoft S.A.
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05007
Kevin O'Connor9521e262008-07-04 13:04:29 -04008#include "biosvar.h" // SET_BDA
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05009#include "util.h" // debug_enter
10#include "disk.h" // floppy_tick
Kevin O'Connor4b60c002008-02-25 22:29:55 -050011#include "cmos.h" // inb_cmos
Kevin O'Connord21c0892008-11-26 17:02:43 -050012#include "pic.h" // eoi_pic1
Kevin O'Connor9521e262008-07-04 13:04:29 -040013#include "bregs.h" // struct bregs
Kevin O'Connor15157a32008-12-13 11:10:37 -050014#include "biosvar.h" // GET_GLOBAL
Kevin O'Connor114592f2009-09-28 21:32:08 -040015#include "usb-hid.h" // usb_check_key
Kevin O'Connor4b60c002008-02-25 22:29:55 -050016
Kevin O'Connor5be04902008-05-18 17:12:06 -040017// RTC register flags
18#define RTC_A_UIP 0x80
Kevin O'Connorf3587592009-02-15 13:02:56 -050019
20#define RTC_B_SET 0x80
21#define RTC_B_PIE 0x40
22#define RTC_B_AIE 0x20
23#define RTC_B_UIE 0x10
24#define RTC_B_BIN 0x04
25#define RTC_B_24HR 0x02
26#define RTC_B_DSE 0x01
27
Kevin O'Connor5be04902008-05-18 17:12:06 -040028
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050029// Bits for PORT_PS2_CTRLB
30#define PPCB_T2GATE (1<<0)
31#define PPCB_SPKR (1<<1)
32#define PPCB_T2OUT (1<<5)
33
34// Bits for PORT_PIT_MODE
35#define PM_SEL_TIMER0 (0<<6)
36#define PM_SEL_TIMER1 (1<<6)
37#define PM_SEL_TIMER2 (2<<6)
38#define PM_SEL_READBACK (3<<6)
39#define PM_ACCESS_LATCH (0<<4)
40#define PM_ACCESS_LOBYTE (1<<4)
41#define PM_ACCESS_HIBYTE (2<<4)
42#define PM_ACCESS_WORD (3<<4)
43#define PM_MODE0 (0<<1)
44#define PM_MODE1 (1<<1)
45#define PM_MODE2 (2<<1)
46#define PM_MODE3 (3<<1)
47#define PM_MODE4 (4<<1)
48#define PM_MODE5 (5<<1)
49#define PM_CNT_BINARY (0<<0)
50#define PM_CNT_BCD (1<<0)
51
52
53/****************************************************************
54 * TSC timer
55 ****************************************************************/
56
Kevin O'Connor6aee52d2009-09-27 20:07:40 -040057#define PIT_TICK_RATE 1193180 // Underlying HZ of PIT
58#define PIT_TICK_INTERVAL 65536 // Default interval for 18.2Hz timer
59#define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
60#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050061
Kevin O'Connor372e0712009-09-09 09:51:31 -040062u32 cpu_khz VAR16VISIBLE;
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050063
64static void
65calibrate_tsc()
66{
67 // Setup "timer2"
68 u8 orig = inb(PORT_PS2_CTRLB);
69 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
70 /* binary, mode 0, LSB/MSB, Ch 2 */
71 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
72 /* LSB of ticks */
73 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
74 /* MSB of ticks */
75 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
76
77 u64 start = rdtscll();
78 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
79 ;
80 u64 end = rdtscll();
81
82 // Restore PORT_PS2_CTRLB
83 outb(orig, PORT_PS2_CTRLB);
84
85 // Store calibrated cpu khz.
86 u64 diff = end - start;
87 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
88 , (u32)start, (u32)end, (u32)diff);
89 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
Kevin O'Connor15157a32008-12-13 11:10:37 -050090 SET_GLOBAL(cpu_khz, hz / 1000);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050091
92 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
93}
94
95static void
Kevin O'Connor89eb6242009-10-22 22:30:37 -040096tscdelay(u64 diff)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050097{
98 u64 start = rdtscll();
99 u64 end = start + diff;
Kevin O'Connor89eb6242009-10-22 22:30:37 -0400100 while (!check_time(end))
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500101 cpu_relax();
102}
103
104void
105ndelay(u32 count)
106{
Kevin O'Connor15157a32008-12-13 11:10:37 -0500107 u32 khz = GET_GLOBAL(cpu_khz);
Kevin O'Connor89eb6242009-10-22 22:30:37 -0400108 tscdelay(count * khz / 1000000);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500109}
110void
111udelay(u32 count)
112{
Kevin O'Connor15157a32008-12-13 11:10:37 -0500113 u32 khz = GET_GLOBAL(cpu_khz);
Kevin O'Connor89eb6242009-10-22 22:30:37 -0400114 tscdelay(count * khz / 1000);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500115}
116void
117mdelay(u32 count)
118{
Kevin O'Connor15157a32008-12-13 11:10:37 -0500119 u32 khz = GET_GLOBAL(cpu_khz);
Kevin O'Connor89eb6242009-10-22 22:30:37 -0400120 tscdelay(count * khz);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500121}
122
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500123// Return the TSC value that is 'msecs' time in the future.
124u64
125calc_future_tsc(u32 msecs)
126{
Kevin O'Connor15157a32008-12-13 11:10:37 -0500127 u32 khz = GET_GLOBAL(cpu_khz);
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500128 return rdtscll() + ((u64)khz * msecs);
129}
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400130u64
131calc_future_tsc_usec(u32 usecs)
132{
133 u32 khz = GET_GLOBAL(cpu_khz);
134 return rdtscll() + ((u64)(khz/1000) * usecs);
135}
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500136
Kevin O'Connor5be04902008-05-18 17:12:06 -0400137
138/****************************************************************
139 * Init
140 ****************************************************************/
141
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500142static int
143rtc_updating()
144{
145 // This function checks to see if the update-in-progress bit
146 // is set in CMOS Status Register A. If not, it returns 0.
147 // If it is set, it tries to wait until there is a transition
148 // to 0, and will return 0 if such a transition occurs. A -1
149 // is returned only after timing out. The maximum period
Kevin O'Connor4f5586c2009-02-16 10:14:10 -0500150 // that this bit should be set is constrained to (1984+244)
151 // useconds, so we wait for 3 msec max.
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500152
Kevin O'Connorf3587592009-02-15 13:02:56 -0500153 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500154 return 0;
Kevin O'Connor4f5586c2009-02-16 10:14:10 -0500155 u64 end = calc_future_tsc(3);
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500156 do {
Kevin O'Connorf3587592009-02-15 13:02:56 -0500157 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500158 return 0;
Kevin O'Connor89eb6242009-10-22 22:30:37 -0400159 } while (!check_time(end));
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500160
161 // update-in-progress never transitioned to 0
162 return -1;
163}
164
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500165static void
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400166pit_setup()
167{
168 // timer0: binary count, 16bit count, mode 2
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500169 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400170 // maximum count of 0000H = 18.2Hz
171 outb(0x0, PORT_PIT_COUNTER0);
172 outb(0x0, PORT_PIT_COUNTER0);
173}
174
Kevin O'Connorf3587592009-02-15 13:02:56 -0500175static void
176init_rtc()
177{
Kevin O'Connor4f5586c2009-02-16 10:14:10 -0500178 outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
Kevin O'Connorf3587592009-02-15 13:02:56 -0500179 u8 regB = inb_cmos(CMOS_STATUS_B);
180 outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
181 inb_cmos(CMOS_STATUS_C);
182 inb_cmos(CMOS_STATUS_D);
183}
184
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400185static u32
186bcd2bin(u8 val)
187{
188 return (val & 0xf) + ((val >> 4) * 10);
189}
190
191void
192timer_setup()
193{
Kevin O'Connor35192dd2008-06-08 19:18:33 -0400194 dprintf(3, "init timer\n");
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500195 calibrate_tsc();
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400196 pit_setup();
197
Kevin O'Connorf3587592009-02-15 13:02:56 -0500198 init_rtc();
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500199 rtc_updating();
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400200 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400201 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400202 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400203 u32 ticks = (hours * 60 + minutes) * 60 + seconds;
204 ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400205 SET_BDA(timer_counter, ticks);
206 SET_BDA(timer_rollover, 0);
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400207
Kevin O'Connord21c0892008-11-26 17:02:43 -0500208 enable_hwirq(0, entry_08);
209 enable_hwirq(8, entry_70);
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400210}
211
Kevin O'Connor5be04902008-05-18 17:12:06 -0400212
213/****************************************************************
214 * Standard clock functions
215 ****************************************************************/
216
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500217// get current clock count
218static void
219handle_1a00(struct bregs *regs)
220{
221 u32 ticks = GET_BDA(timer_counter);
222 regs->cx = ticks >> 16;
223 regs->dx = ticks;
224 regs->al = GET_BDA(timer_rollover);
225 SET_BDA(timer_rollover, 0); // reset flag
Kevin O'Connor6c781222008-03-09 12:19:23 -0400226 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500227}
228
229// Set Current Clock Count
230static void
231handle_1a01(struct bregs *regs)
232{
233 u32 ticks = (regs->cx << 16) | regs->dx;
234 SET_BDA(timer_counter, ticks);
235 SET_BDA(timer_rollover, 0); // reset flag
Kevin O'Connor15157a32008-12-13 11:10:37 -0500236 // XXX - should use set_code_success()?
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500237 regs->ah = 0;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400238 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500239}
240
241// Read CMOS Time
242static void
243handle_1a02(struct bregs *regs)
244{
245 if (rtc_updating()) {
Kevin O'Connor6c781222008-03-09 12:19:23 -0400246 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500247 return;
248 }
249
250 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
251 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
252 regs->ch = inb_cmos(CMOS_RTC_HOURS);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500253 regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500254 regs->ah = 0;
255 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400256 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500257}
258
259// Set CMOS Time
260static void
261handle_1a03(struct bregs *regs)
262{
263 // Using a debugger, I notice the following masking/setting
264 // of bits in Status Register B, by setting Reg B to
265 // a few values and getting its value after INT 1A was called.
266 //
267 // try#1 try#2 try#3
268 // before 1111 1101 0111 1101 0000 0000
269 // after 0110 0010 0110 0010 0000 0010
270 //
271 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
272 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
273 if (rtc_updating()) {
274 init_rtc();
275 // fall through as if an update were not in progress
276 }
277 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
278 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
279 outb_cmos(regs->ch, CMOS_RTC_HOURS);
280 // Set Daylight Savings time enabled bit to requested value
Kevin O'Connorf3587592009-02-15 13:02:56 -0500281 u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
282 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500283 outb_cmos(val8, CMOS_STATUS_B);
284 regs->ah = 0;
285 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400286 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500287}
288
289// Read CMOS Date
290static void
291handle_1a04(struct bregs *regs)
292{
293 regs->ah = 0;
294 if (rtc_updating()) {
Kevin O'Connor6c781222008-03-09 12:19:23 -0400295 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500296 return;
297 }
298 regs->cl = inb_cmos(CMOS_RTC_YEAR);
299 regs->dh = inb_cmos(CMOS_RTC_MONTH);
300 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500301 if (CONFIG_COREBOOT) {
302 if (regs->cl > 0x80)
303 regs->ch = 0x19;
304 else
305 regs->ch = 0x20;
306 } else {
307 regs->ch = inb_cmos(CMOS_CENTURY);
308 }
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500309 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400310 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500311}
312
313// Set CMOS Date
314static void
315handle_1a05(struct bregs *regs)
316{
317 // Using a debugger, I notice the following masking/setting
318 // of bits in Status Register B, by setting Reg B to
319 // a few values and getting its value after INT 1A was called.
320 //
321 // try#1 try#2 try#3 try#4
322 // before 1111 1101 0111 1101 0000 0010 0000 0000
323 // after 0110 1101 0111 1101 0000 0010 0000 0000
324 //
325 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
326 // My assumption: RegB = (RegB & 01111111b)
327 if (rtc_updating()) {
328 init_rtc();
Kevin O'Connor6c781222008-03-09 12:19:23 -0400329 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500330 return;
331 }
332 outb_cmos(regs->cl, CMOS_RTC_YEAR);
333 outb_cmos(regs->dh, CMOS_RTC_MONTH);
334 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500335 if (!CONFIG_COREBOOT)
336 outb_cmos(regs->ch, CMOS_CENTURY);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400337 // clear halt-clock bit
338 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500339 outb_cmos(val8, CMOS_STATUS_B);
340 regs->ah = 0;
341 regs->al = val8; // AL = val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400342 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500343}
344
345// Set Alarm Time in CMOS
346static void
347handle_1a06(struct bregs *regs)
348{
349 // Using a debugger, I notice the following masking/setting
350 // of bits in Status Register B, by setting Reg B to
351 // a few values and getting its value after INT 1A was called.
352 //
353 // try#1 try#2 try#3
354 // before 1101 1111 0101 1111 0000 0000
355 // after 0110 1111 0111 1111 0010 0000
356 //
357 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
358 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
359 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
360 regs->ax = 0;
Kevin O'Connorf3587592009-02-15 13:02:56 -0500361 if (val8 & RTC_B_AIE) {
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500362 // Alarm interrupt enabled already
Kevin O'Connor6c781222008-03-09 12:19:23 -0400363 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500364 return;
365 }
366 if (rtc_updating()) {
367 init_rtc();
368 // fall through as if an update were not in progress
369 }
370 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
371 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
372 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500373 // enable Status Reg B alarm bit, clear halt clock bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400374 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
Kevin O'Connor6c781222008-03-09 12:19:23 -0400375 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500376}
377
378// Turn off Alarm
379static void
380handle_1a07(struct bregs *regs)
381{
382 // Using a debugger, I notice the following masking/setting
383 // of bits in Status Register B, by setting Reg B to
384 // a few values and getting its value after INT 1A was called.
385 //
386 // try#1 try#2 try#3 try#4
387 // before 1111 1101 0111 1101 0010 0000 0010 0010
388 // after 0100 0101 0101 0101 0000 0000 0000 0010
389 //
390 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
391 // My assumption: RegB = (RegB & 01010111b)
392 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
393 // clear clock-halt bit, disable alarm bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400394 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500395 regs->ah = 0;
396 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400397 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500398}
399
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500400// Unsupported
401static void
402handle_1aXX(struct bregs *regs)
403{
Kevin O'Connor6c781222008-03-09 12:19:23 -0400404 set_fail(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500405}
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500406
407// INT 1Ah Time-of-day Service Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500408void VISIBLE16
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500409handle_1a(struct bregs *regs)
410{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400411 debug_enter(regs, DEBUG_HDL_1a);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500412 switch (regs->ah) {
413 case 0x00: handle_1a00(regs); break;
414 case 0x01: handle_1a01(regs); break;
415 case 0x02: handle_1a02(regs); break;
416 case 0x03: handle_1a03(regs); break;
417 case 0x04: handle_1a04(regs); break;
418 case 0x05: handle_1a05(regs); break;
419 case 0x06: handle_1a06(regs); break;
420 case 0x07: handle_1a07(regs); break;
421 case 0xb1: handle_1ab1(regs); break;
422 default: handle_1aXX(regs); break;
423 }
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500424}
425
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500426// INT 08h System Timer ISR Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500427void VISIBLE16
Kevin O'Connored128492008-03-11 11:14:59 -0400428handle_08()
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500429{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400430 debug_isr(DEBUG_ISR_08);
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500431
432 floppy_tick();
433
434 u32 counter = GET_BDA(timer_counter);
435 counter++;
436 // compare to one days worth of timer ticks at 18.2 hz
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400437 if (counter >= TICKS_PER_DAY) {
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500438 // there has been a midnight rollover at this point
439 counter = 0;
440 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
441 }
442
443 SET_BDA(timer_counter, counter);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500444
Kevin O'Connor114592f2009-09-28 21:32:08 -0400445 usb_check_key();
446
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500447 // chain to user timer tick INT #0x1c
Kevin O'Connora83ff552009-01-01 21:00:59 -0500448 u32 eax=0, flags;
449 call16_simpint(0x1c, &eax, &flags);
Kevin O'Connored128492008-03-11 11:14:59 -0400450
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400451 eoi_pic1();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500452}
453
Kevin O'Connor5be04902008-05-18 17:12:06 -0400454
455/****************************************************************
456 * Periodic timer
457 ****************************************************************/
458
459static int
Kevin O'Connor72743f12008-05-24 23:04:09 -0400460set_usertimer(u32 usecs, u16 seg, u16 offset)
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500461{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400462 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
463 return -1;
464
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500465 // Interval not already set.
466 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
Kevin O'Connor9f985422009-09-09 11:34:39 -0400467 SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
Kevin O'Connor72743f12008-05-24 23:04:09 -0400468 SET_BDA(user_wait_timeout, usecs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500469
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500470 // Turn on the Periodic Interrupt timer
471 u8 bRegister = inb_cmos(CMOS_STATUS_B);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400472 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500473
Kevin O'Connor5be04902008-05-18 17:12:06 -0400474 return 0;
475}
476
477static void
478clear_usertimer()
479{
480 // Turn off status byte.
481 SET_BDA(rtc_wait_flag, 0);
482 // Clear the Periodic Interrupt.
483 u8 bRegister = inb_cmos(CMOS_STATUS_B);
484 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
485}
486
Kevin O'Connor5be04902008-05-18 17:12:06 -0400487#define RET_ECLOCKINUSE 0x83
488
Kevin O'Connord21c0892008-11-26 17:02:43 -0500489// Wait for CX:DX microseconds
Kevin O'Connor5be04902008-05-18 17:12:06 -0400490void
491handle_1586(struct bregs *regs)
492{
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500493 // Use the rtc to wait for the specified time.
494 u8 statusflag = 0;
495 u32 count = (regs->cx << 16) | regs->dx;
496 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
497 if (ret) {
Kevin O'Connor5be04902008-05-18 17:12:06 -0400498 set_code_fail(regs, RET_ECLOCKINUSE);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500499 return;
500 }
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500501 while (!statusflag)
Kevin O'Connoree2efa72009-09-20 15:33:08 -0400502 wait_irq();
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500503 set_success(regs);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400504}
505
506// Set Interval requested.
507static void
508handle_158300(struct bregs *regs)
509{
510 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
511 if (ret)
512 // Interval already set.
513 set_code_fail(regs, RET_EUNSUPPORTED);
514 else
515 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500516}
517
518// Clear interval requested
519static void
520handle_158301(struct bregs *regs)
521{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400522 clear_usertimer();
523 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500524}
525
526static void
527handle_1583XX(struct bregs *regs)
528{
Kevin O'Connor6c781222008-03-09 12:19:23 -0400529 set_code_fail(regs, RET_EUNSUPPORTED);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500530 regs->al--;
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500531}
532
533void
534handle_1583(struct bregs *regs)
535{
536 switch (regs->al) {
537 case 0x00: handle_158300(regs); break;
538 case 0x01: handle_158301(regs); break;
539 default: handle_1583XX(regs); break;
540 }
541}
542
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400543#define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
544
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500545// int70h: IRQ8 - CMOS RTC
Kevin O'Connor19786762008-03-05 21:09:59 -0500546void VISIBLE16
Kevin O'Connored128492008-03-11 11:14:59 -0400547handle_70()
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500548{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400549 debug_isr(DEBUG_ISR_70);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500550
551 // Check which modes are enabled and have occurred.
552 u8 registerB = inb_cmos(CMOS_STATUS_B);
553 u8 registerC = inb_cmos(CMOS_STATUS_C);
554
Kevin O'Connor5be04902008-05-18 17:12:06 -0400555 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500556 goto done;
Kevin O'Connorf3587592009-02-15 13:02:56 -0500557 if (registerC & RTC_B_AIE) {
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500558 // Handle Alarm Interrupt.
Kevin O'Connora83ff552009-01-01 21:00:59 -0500559 u32 eax=0, flags;
560 call16_simpint(0x4a, &eax, &flags);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500561 }
Kevin O'Connorf3587592009-02-15 13:02:56 -0500562 if (!(registerC & RTC_B_PIE))
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500563 goto done;
564
565 // Handle Periodic Interrupt.
566
567 if (!GET_BDA(rtc_wait_flag))
568 goto done;
569
570 // Wait Interval (Int 15, AH=83) active.
571 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400572 if (time < USEC_PER_RTC) {
Kevin O'Connor5be04902008-05-18 17:12:06 -0400573 // Done waiting - write to specified flag byte.
Kevin O'Connor9f985422009-09-09 11:34:39 -0400574 struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
575 u16 ptr_seg = segoff.seg;
576 u8 *ptr_far = (u8*)(segoff.offset+0);
577 u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
578 SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400579
580 clear_usertimer();
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500581 } else {
582 // Continue waiting.
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400583 time -= USEC_PER_RTC;
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500584 SET_BDA(user_wait_timeout, time);
585 }
586
587done:
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400588 eoi_pic2();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500589}