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review.coreboot.org / coreboot / 9631016660423d0585a1 / src / soc / imgtec / pistachio / Makefile.inc
  1. 3bdd45e soc/imgtec/pistachio: Implement hard_reset() by Stefan Reinauer · 9 years ago
  2. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  3. d972f78 linking: link bootblock.elf with .data and .bss sections again by Aaron Durbin · 9 years ago
  4. 3fa1ad0 pistachio: add DDR3 initialization code by Ionela Voinescu · 9 years ago
  5. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  6. aae53ab kbuild: automatically include SOCs by Stefan Reinauer · 9 years ago
  7. d6aaca9 pistachio: add DDR2 initialization code by Ionela Voinescu · 9 years ago
  8. b3f666b urara: Configure clocks and MFIOs by Ionela Voinescu · 9 years ago
  9. f3bc026 pistachio: add SOC descriptor by Vadim Bendebury · 10 years ago
  10. 52a8879 pistachio: implement timer support by Vadim Bendebury · 10 years ago
  11. 0812568 pistachio: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  12. ec5e5e0 New mechanism to define SRAM/memory map with automatic bounds checking by Julius Werner · 10 years ago
  13. 146d05d imgtec/pistachio: Bring uart driver to modern standards by Patrick Georgi · 9 years ago
  14. 49aad6b soc/imgtec/pistachio: Add IMGTEC SPI controller driver by Ionela Voinescu · 10 years ago
  15. 2d510d0 urara: use proper SOC name by Vadim Bendebury · 10 years ago[Renamed (96%) from src/soc/imgtec/danube/Makefile.inc]
  16. f16b082 danube: Use the generic timer interface by Vadim Bendebury · 10 years ago
  17. c7b3f72 danube: use SOC specific rom stage code by Vadim Bendebury · 10 years ago
  18. b2e465d danube: prepare SOC directory for urara by Vadim Bendebury · 10 years ago
  19. c1081a4 imgtec/danube: Add support for ImgTec Danube SoC by Paul Burton · 10 years ago