pistachio: implement timer support
C0_COUNT register is a free running counter clocked by the CPU
frequency divided by two. On the FPGA board it results in 25 MHz, on
real SOCs it will have to be figured out later.
Some magic addresses and numbers are used to find out if the code is
running on the FPGA board.
timestamp_get() and timer_monotonic_get() are kept in the same file.
The CPU initialization makes sure that CO COUNT is in fact enabled and
starts from zero.
TEST=with timer enabled, the startup code properly initializes UART
and prints the coreboot bootblock banner message on the serial
Signed-off-by: Stefan Reinauer <email@example.com>
Original-Signed-off-by: Vadim Bendebury <firstname.lastname@example.org>
Original-Reviewed-by: Aaron Durbin <email@example.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <firstname.lastname@example.org>
5 files changed