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Angel Pons4b429832020-04-02 23:48:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Martin Roth5474eb12018-05-26 19:22:33 -06002
Kyösti Mälkkide640782019-12-03 07:30:26 +02003#include <arch/bootblock.h>
Angel Pons1318ab42021-01-20 13:31:09 +01004#include <assert.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02005#include <device/pci_ops.h>
Angel Pons1318ab42021-01-20 13:31:09 +01006#include <types.h>
Arthur Heymans99e578e2019-01-15 20:14:33 +01007#include "pineview.h"
8
Angel Pons1318ab42021-01-20 13:31:09 +01009static uint32_t encode_pciexbar_length(void)
10{
Shelley Chen4e9bb332021-10-20 15:43:45 -070011 switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
Angel Pons1318ab42021-01-20 13:31:09 +010012 case 256: return 0 << 1;
13 case 128: return 1 << 1;
14 case 64: return 2 << 1;
15 default: return dead_code_t(uint32_t);
16 }
17}
Damien Zammit62477932015-05-03 21:34:38 +100018
Arthur Heymans99e578e2019-01-15 20:14:33 +010019void bootblock_early_northbridge_init(void)
Damien Zammit62477932015-05-03 21:34:38 +100020{
Shelley Chen4e9bb332021-10-20 15:43:45 -070021 const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
Angel Pons1318ab42021-01-20 13:31:09 +010022 pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
Damien Zammit62477932015-05-03 21:34:38 +100023}