blob: 1c04c28b98893d1ab85f4021db6b75f4fd7222a6 [file] [log] [blame]
Damien Zammit62477932015-05-03 21:34:38 +10001#include <arch/io.h>
2#define PCIEXBAR 0x60
3
4static void bootblock_northbridge_init(void)
5{
6 pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
7 CONFIG_MMCONF_BASE_ADDRESS | 4 | 1);
8}