| Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 3 | |
| Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 4 | #include <arch/bootblock.h> |
| Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
| Arthur Heymans | 99e578e | 2019-01-15 20:14:33 +0100 | [diff] [blame] | 6 | #include "pineview.h" |
| 7 | |
| Damien Zammit | 2cfab90 | 2016-01-18 16:39:51 +1100 | [diff] [blame] | 8 | #define MMCONF_256_BUSSES 16 |
| 9 | #define ENABLE 1 |
| Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 10 | |
| Arthur Heymans | 99e578e | 2019-01-15 20:14:33 +0100 | [diff] [blame] | 11 | void bootblock_early_northbridge_init(void) |
| Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 12 | { |
| Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 13 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, |
| Damien Zammit | 2cfab90 | 2016-01-18 16:39:51 +1100 | [diff] [blame] | 14 | CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); |
| Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 15 | } |