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review.coreboot.org / coreboot / refs/heads/main / . / src / northbridge / intel / i945 / raminit.h
blob: 22c4faf653385405a32fcda390dda273ddc36e6c [file] [log] [blame]
Angel Pons4b429832020-04-02 23:48:50 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]2
3#ifndef RAMINIT_H
4#define RAMINIT_H
5
Elyes Haouas49446092022-09-28 14:14:05 +0200[diff] [blame]6#include <types.h>
7
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]8#define DIMM_SOCKETS 2
9
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]10#define DIMM_TCO_BASE 0x30
11
12/* Burst length is always 8 */
13#define BURSTLENGTH 8
14
15struct sys_info {
16 u16 memory_frequency; /* 400, 533 or 667 */
Elyes HAOUASd9e65432016-12-01 19:59:12 +0100[diff] [blame]17 u16 fsb_frequency; /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */
Arthur Heymans0ab49042017-02-06 22:40:14 +0100[diff] [blame]18 u32 tclk;
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]19
Arthur Heymans0ab49042017-02-06 22:40:14 +0100[diff] [blame]20 u8 trp;
21 u8 trcd;
22 u8 tras;
23 u8 trfc;
24 u8 twr;
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]25
26 u8 cas; /* 3, 4 or 5 */
27 u8 refresh; /* 0 = 15.6us, 1 = 7.8us */
28
Elyes Haouas49446092022-09-28 14:14:05 +0200[diff] [blame]29 bool dual_channel;
30 bool interleaved;
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]31
32 u8 mvco4x; /* 0 (8x) or 1 (4x) */
Elyes Haouasd9dade32022-10-07 12:05:38 +0200[diff] [blame]33 bool clkcfg_bit7;
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]34 u8 boot_path;
Stefan Reinauer71a3d962009-07-21 21:44:24 +0000[diff] [blame]35#define BOOT_PATH_NORMAL 0
36#define BOOT_PATH_RESET 1
37#define BOOT_PATH_RESUME 2
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]38
39 u8 package; /* 0 = planar, 1 = stacked */
40#define SYSINFO_PACKAGE_PLANAR 0x00
41#define SYSINFO_PACKAGE_STACKED 0x01
42 u8 dimm[2 * DIMM_SOCKETS];
Arthur Heymans0ab49042017-02-06 22:40:14 +0100[diff] [blame]43 u8 rows[2 * DIMM_SOCKETS];
44 u8 cols[2 * DIMM_SOCKETS];
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]45#define SYSINFO_DIMM_X16DS 0x00
46#define SYSINFO_DIMM_X8DS 0x01
47#define SYSINFO_DIMM_X16SS 0x02
48#define SYSINFO_DIMM_X8DDS 0x03
49#define SYSINFO_DIMM_NOT_POPULATED 0x04
50
51 u8 banks[2 * DIMM_SOCKETS];
Elyes Haouas26fc2a42022-10-07 11:25:25 +0200[diff] [blame]52 size_t banksize[2 * 2 * DIMM_SOCKETS];
Sven Schnelle541269b2011-02-21 09:39:17 +0000[diff] [blame]53 const u8 *spd_addresses;
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]54
Stefan Reinauer6a001132017-07-13 02:20:27 +0200[diff] [blame]55} __packed;
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]56
Stefan Reinauerde3206a2010-02-22 06:09:43 +0000[diff] [blame]57void receive_enable_adjust(struct sys_info *sysinfo);
Sven Schnelle541269b2011-02-21 09:39:17 +0000[diff] [blame]58void sdram_initialize(int boot_path, const u8 *sdram_addresses);
Elyes HAOUAS8273e132020-03-10 22:17:12 +0100[diff] [blame]59int fixup_i945gm_errata(void);
Stefan Reinauer278534d2008-10-29 04:51:07 +0000[diff] [blame]60#endif /* RAMINIT_H */